RECESS GATE TRANSISTOR

• US 20090173994A1
• Filed: 10/14/2008
• Published: 07/09/2009
• Est. Priority Date: 01/07/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Si-Hyung, Choi, Si-Young, Woo, Dongsoo, Kang, Sangbom, Hwang, Heedon, Min, Ji-Young
• Granted Patent: US 8,012,828 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302

Abstract

A recess gate of a semiconductor device is provided, comprising: a substrate having a recess formed therein; a metal layer formed at the bottom of the recess; a polysilicon layer formed over the metal layer; and a source region and a drain region formed adjacent to the polysilicon layer and spaced from the metal layer. A method of forming a semiconductor device is also provided, comprising forming a substrate and a source and drain layer; forming a recess and depositing a gate insulation layer therein; forming a first conductive layer on the gate insulation layer; forming a first conductive layer pattern by recessing the first conductive layer; forming a second conductive layer on the first conductive layer pattern; forming a second conductive layer pattern by patterning the second conductive layer to overlap the source and drain layer; depositing an insulating layer on the second conductive layer pattern and the source and drain layer; and planarizing the insulating layer to form a cap on the second conductive layer pattern.

Claims

1. A recess gate of a semiconductor device, comprising:

a substrate having a recess formed therein;

a metal layer formed at the bottom of the recess;

a polysilicon layer formed over the metal layer; and

a source region and a drain region formed adjacent to the polysilicon layer and spaced from the metal layer.

2. The semiconductor device of claim 1, wherein the recess gate is part of an NMOS device and the metal layer has a workfunction equal to or greater than a workfunction of the polysilicon layer.

3. The semiconductor device of claim 1, wherein the recess gate is part of a PMOS device and the metal layer has a workfunction equal to or less than a workfunction of the polysilicon layer.

4. The semiconductor device of claim 1, wherein the metal layer is selected from a group consisting of Ti, TiN, W, WN, Ta, TaN, Co, C, Rb, or Ru.

5. The semiconductor device of claim 1, wherein the metal layer has a thickness of about 500 A. to about 1,500 A.

6. The semiconductor device of claim 1, wherein the thickness of the polysilicon layer is equal to or greater than the thickness of the metal layer.

7. A recess gate of a semiconductor device, comprising:

a substrate having a recess formed therein;

a first conductive layer formed at the bottom of the recess;

a second conductive layer formed over the first conductive layer; and

a source region and a drain region formed adjacent to the second conductive layer and spaced from the first conductive layer.

8. The semiconductor device of claim 7, wherein the recess gate is part of an NMOS device and the first conductive layer has a workfunction equal to or greater than a workfunction of the second conductive layer.

9. The semiconductor device of claim 7, wherein the recess gate is part of a PMOS device and the first conductive layer has a workfunction equal to or less than a workfunction of the second conductive layer.

10. The semiconductor device of claim 7, wherein the first conductive layer is selected from a group consisting of Ti, TiN, W, WN, Ta, TaN, Co, C, Rb, or Ru.

11. The semiconductor device of claim 7, wherein the second conductive layer is a polysilicon.

12. The semiconductor device of claim 11, further including an ohmic layer above the second conductive layer.

13. The semiconductor device of claim 12, wherein the ohmic layer is selected from a group consisting of TiSi, Ta, Tasi, CoSi, or WSi.

14. The semiconductor device of claim 11, further including a capping metal layer.

15. The semiconductor device of claim 14, wherein the capping metal layer is selected from a group consisting of Ti, TiN, Ta, TaN, WN, or W.

16. The semiconductor device of claim 7, wherein the second conductive layer is selected from a group consisting of Ti, TiN, W, WN, Ta, TaN, Co, C, Rb, or Ru.

17. The semiconductor device of claim 7, wherein the thickness of the second conductive layer is equal to or greater than the thickness of the first conductive layer.

18. A method of forming a semiconductor device, comprising:

forming a substrate and a source and drain layer;

forming a recess and depositing a gate insulation layer therein;

forming a first conductive layer on the gate insulation layer;

forming a first conductive layer pattern by recessing the first conductive layer;

forming a second conductive layer on the first conductive layer pattern; and

forming a second conductive layer pattern by patterning the second conductive layer.

19. The method of claim 18, wherein the first conductive layer pattern is metallic and the second conductive layer pattern is polysilicon.

20. The method according to claim 18, wherein the second conductive layer pattern includes a portion disposed adjacent to the source and drain layer and the first conductive layer pattern is disposed spaced apart from the source and drain layer.

21. The method of claim 18, wherein the first conductive layer pattern and the second conductive layer pattern are both metallic.

22. The method of claim 18, wherein the source and drain layer and the recess form a part of an NMOS device and the first conductive layer pattern has a workfunction equal to or greater than a workfunction of the second conductive layer pattern.

23. The method of claim 18, wherein the source and drain layer and the recess is part of a PMOS device and the first conductive layer pattern has a workfunction equal to or less than a workfunction of the second conductive layer pattern.

24. The method of claim 18, wherein the first conductive layer is selected from a group consisting of Ti, TiN, W, WN, Ta, TaN, Co, C, Rb, or Ru.

25. The method of forming a semiconductor device according to claim 18, further including:

depositing an insulating layer on the second conductive layer pattern;

etching the insulating layer to expose the second conductive layer pattern and forming a spacer layer adjacent to the source and drain layer; and

forming a third conductive layer on the second conductive layer pattern and the spacer layer.

26. The method of claim 25, wherein the spacer layer is an oxide or a nitride.

27. The method of claim 25, wherein the first conductive layer pattern is a metal and the second conductive layer pattern is a polysilicon.

28. The method of claim 25, wherein the first conductive layer pattern and the second conductive layer pattern are both metallic.

29. A method of forming a semiconductor device, comprising:

forming a substrate and a source and drain layer;

forming a recess and depositing a gate insulation layer therein;

forming a first conductive layer on the gate insulation layer;

forming a first conductive layer pattern by recessing the first conductive layer;

forming a second conductive layer on the first conductive layer pattern;

forming a second conductive layer pattern by patterning the second conductive layer to overlap the source and drain layer;

depositing an insulating layer on the second conductive layer pattern and the source and drain layer; and

planarizing the insulating layer to form a cap on the second conductive layer pattern.

30. The method according to claim 29, wherein the second conductive layer pattern includes a portion disposed adjacent to the source and drain layer and the first conductive layer pattern is disposed spaced apart from the source and drain layer.

31. The method of claim 29, wherein the source and drain layer and the recess form a part of an NMOS device and the first conductive layer pattern has a workfunction equal to or greater than a workfunction of the second conductive layer pattern.

32. The method of claim 29, wherein the source and drain layer and the recess is part of a PMOS device and the first conductive layer pattern has a workfunction equal to or less than a workfunction of the second conductive layer pattern.

33. The method of claim 29, wherein the first conductive layer is selected from a group consisting of Ti, TiN, W, WN, Ta, TaN, Co, C, Rb, or Ru.

34. The method of claim 29, wherein the second conductive layer is polysilicon.

35. A memory system comprising:

a memory controller and a memory device, the memory controller controls the memory device to read or write data from/into the memory in response to a read/write request of a host, wherein the memory device includes a memory cell region having a plurality of transistors, each transistor comprising;

a substrate having a recess formed therein;

a first conductive layer formed at the bottom of the recess;

a second conductive layer formed over the first conductive layer; and

a source region and a drain region formed adjacent to the second conductive layer and spaced from the first conductive layer.

36. The memory system of claim 35, wherein the first conductive layer is a metal selected from a group consisting of Ti, TiN, W, WN, Ta, TaN, Co, C, Rb, or Ru.

37. The memory system of claim 36, wherein the second conductive layer is a polysilicon.

38. The memory system of claim 35, wherein the host is a mobile device or a processing device having a processor.

39. The memory system of claim 35, further including a wireless interface for communicating with another cellular device.