INTEGRATED CIRCUIT INCLUDING ISOLATION REGIONS SUBSTANTIALLY THROUGH SUBSTRATE

• US 20090174027A1
• Filed: 01/09/2008
• Published: 07/09/2009
• Est. Priority Date: 01/09/2008
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Tilke, Armin
• Granted Patent: US 7,816,759 B2
• Time in Patent Office: Days
• US Class Current: 257/513
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 23/58 Structural electrical arrangements for semiconductor devices not otherwise provided for , e.g. in combination with batteries H01L23/49593, H01L23/49596 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An integrated circuit including a substrate and trench isolation regions. The substrate supports a device. The trench isolation regions are configured to laterally isolate the device. The trench isolation regions extend substantially through the substrate.

Claims

1. An integrated circuit comprising:

a substrate that supports a device; and

trench isolation regions configured to laterally isolate the device, wherein the trench isolation regions extend substantially through the substrate.

2. The integrated circuit of claim 1, comprising:

a backside that has been backside polished to the trench isolation regions.

3. The integrated circuit of claim 1, comprising:

a backside; and

an insulator situated on the backside, wherein the insulator is situated on the substrate and the trench isolation regions.

4. The integrated circuit of claim 3, wherein the insulator is a nitride dielectric.

5. The integrated circuit of claim 1, comprising:

an epitaxial layer, wherein the trench isolation regions extend substantially from the epitaxial layer through the substrate.

6. The integrated circuit of claim 1, comprising:

an epitaxial layer in contact with the substrate, wherein the substrate is one of an n-plus substrate and a p-plus substrate.

7. The integrated circuit of claim 1, comprising:

an epitaxial layer; and

a buried layer between the substrate and the epitaxial layer.

8. The integrated circuit of claim 1, wherein the integrated circuit is part of a semiconductor wafer.

9. An integrated circuit comprising:

a substrate;

an n-plus buried layer in contact with the substrate;

an epitaxial layer in contact with the n-plus buried layer; and

deep trench isolation regions configured to laterally isolate devices in the epitaxial layer.

10. The integrated circuit of claim 9, comprising:

a sinker configured to extend through the epitaxial layer and contact the n-plus buried layer.

11. The integrated circuit of claim 9, wherein each of the deep trench isolation regions comprise:

an n-doped dielectric liner.

12. The integrated circuit of claim 11, wherein the n-doped dielectric liner has been driven-out and into the epitaxial layer, the n-plus buried layer, and the substrate.

13. The integrated circuit of claim 9, wherein each of the deep trench isolation regions comprise one of:

an n-plus polysilicon liner, carbon, and silicide.

14. The integrated circuit of claim 13, wherein the n-plus polysilicon liner has been driven-out and into the epitaxial layer, the n-plus buried layer, and the substrate.

15. An integrated circuit comprising:

a substrate that supports a device; and

a deep trench isolation region extending through at least a portion of the substrate, wherein the deep trench isolation region comprises a conductive material lining a sidewall surface of the deep trench isolation region.

16. The integrated circuit of claim 15, wherein the deep trench isolation region extends through the substrate.

17. A method of manufacturing an integrated circuit, comprising:

providing a substrate that supports a device;

forming deep trench isolation regions through at least a portion of the substrate; and

polishing the backside of the integrated circuit.

18. The method of claim 17, wherein polishing the backside of the integrated circuit comprises:

polishing the backside of the integrated circuit to the deep trench isolation regions.

19. The method of claim 17, comprising:

insulating the backside of the integrated circuit.

20. The method of claim 17, comprising:

lining the deep trench isolation regions with an n-doped material; and

driving-out the n-doped material.

21. The method of claim 20, comprising:

stripping the n-doped material from the deep trench isolation regions.

22. A method of manufacturing an integrated circuit, comprising:

providing an n-type substrate;

providing an n-plus buried layer in contact with the n-type substrate;

providing an epitaxial layer in contact with the n-plus buried layer; and

isolating devices in the epitaxial layer via deep trench isolation regions.

23. The method of claim 22, comprising:

contacting the n-plus buried layer via the deep trench isolation regions.