DRAM HAVING DEEP TRENCH CAPACITORS WITH LIGHTLY DOPED BURIED PLATES

• US 20090174031A1
• Filed: 01/07/2008
• Published: 07/09/2009
• Est. Priority Date: 01/07/2008
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Faltermeier, Johnathan E., Cheng, Kangguo, Wang, Geng, Parries, Paul C.
• Granted Patent: US 7,923,815 B2
• Time in Patent Office: Days
• US Class Current: 257/532
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate

Abstract

By controlling buried plate doping level and bias condition, different capacitances can be obtained from capacitors on the same chip with the same layout and deep trench process. The capacitors may be storage capacitors of DRAM/eDRAM cells. The doping concentration may be less than 3E19cm−3, a voltage difference between the biases of the buried electrodes may be at least 0.5V, and a capacitance of one capacitor may be at least 1.2 times, such as 2.0 times the capacitance of another capacitor.

Claims

1. A microelectronic element comprising:

a semiconductor substrate;

a first capacitor comprising two electrodes, one of which is a buried plate, and a dielectric layer sandwiched between the two electrodes;

a second capacitor comprising two electrodes, one of which is a buried plate, and a dielectric layer sandwiched between the two electrodes;

a first contact plug for applying a first bias voltage to the buried plate of the first capacitor; and

a second contact plug for applying a second bias voltage, different than the first bias voltage, to the buried plate of the second capacitor.

2. The microelectronic element of claim 1, wherein:

the two capacitors have different capacitances.

3. The microelectronic element of claim 1, wherein:

the buried plates of the first and second capacitors are located in a doped region of the substrate having a doping concentration; and

the doping concentration is less than 3E19cm−

3.

4. The microelectronic element of claim 3, wherein:

the doping concentration is less than 1E19cm−

3.

5. The microelectronic element of claim 3, wherein:

the doping concentration is between 1E13 and 1E19cm−

3.

6. The microelectronic element of claim 3, wherein:

the doping concentration is between 1E17 and 1E19cm−

3.

7. The microelectronic element of claim 1, wherein:

a voltage difference between the biases of the buried plates of the first capacitor and the second capacitor is at least 1.0V.

8. The microelectronic element of claim 1, wherein:

a voltage difference between the biases of the buried plates of the first capacitor and the second capacitor is at least 0.5V.

9. The microelectronic element of claim 1, wherein:

the buried plate of the first capacitor is disposed in a first doped region of the substrate having a first doping concentration; and

the buried plate of the second capacitor is disposed in a second doped region of the substrate having a second doping concentration which is different than the first doping concentration.

10. The microelectronic element of claim 1, wherein:

the capacitance of the first capacitor at least 2.0 times the capacitance of the second capacitor.

11. The microelectronic element of claim 1, wherein:

the capacitance of the first capacitor at least 1.2 times the capacitance of the second capacitor.

12. The microelectronic element of claim 1, wherein:

the buried plates are each located in a doped region of the substrate having a doping concentration;

the doping concentration is less than 3E19cm−

3;

a voltage difference between the biases of the buried plates of the first capacitor and the second capacitor is at least 0.5V; and

the capacitance of the first capacitor at least 1.2 times the capacitance of the second capacitor.

13. The microelectronic element of claim 1, wherein:

the first and second capacitors are trench capacitors.

14. The microelectronic element of claim 1, wherein:

the first and second capacitors are storage capacitors of DRAM/eDRAM cells.

15. A method of obtaining different capacitance values for a first and a second capacitor formed in a substrate and having substantially identical physical characteristics as one another, comprising:

formed a first and a second capacitor, substantially physically identical to one another, both of the capacitors having lightly doped buried plates;

operating the first capacitor with a bias voltage different than a bias voltage for the second capacitor.

16. The method of claim 15, wherein:

the second capacitor has a capacitance of at least 1.2 times the first capacitor.

17. The method of claim 15, wherein:

the capacitors are deep trench capacitors having buried plates; and

the buried plates have a doping concentration between 1E13 and 3E19 atoms per cubic centimeter.

18. The method of claim 15, further comprising:

for at least one of the first and second capacitors, changing its bias voltage, hence its capacitance, from time-to-time.

19. A design structure embodied in a machine readable medium for designing, manufacturing, or testing a design, the design structure comprising:

a semiconductor substrate;

a first capacitor comprising two electrodes, one of which is a buried plate, and a dielectric layer sandwiched between the two electrodes; and

a second capacitor comprising two electrodes, one of which is a buried plate, and a dielectric layer sandwiched between the two electrodes;

a first contact plug for applying a first bias voltage to the buried plate of the first capacitor; and

a second contact plug for applying a second bias voltage, different than the first bias voltage, to the buried plate of the second capacitor.

20. The design structure of claim 19, wherein:

the design structure comprises a netlist, which describes the design;

the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits; and

the design structure includes at least one of test data files, characterization data, verification data, and design specifications.