PLASMA CURING OF PATTERNING MATERIALS FOR AGGRESSIVELY SCALED FEATURES
First Claim
1. A method of fabricating a semiconductor structure having reduced line edge roughness/line width roughness values, comprising:
- exposing at least one preprocessed patterning material located on a substrate to vacuum ultra violet (VUV) emissions to induce crosslinking of said at least one preprocessed patterning material, said VUV emissions are generated by an inert species containing plasma.
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Abstract
A methodology is disclosed that enables the fabrication of semiconductor devices (i.e., STI structures, gates, and interconnects) with significantly reduced line edge roughness (LER) and line width roughness (LEW) post lithography patterning. The inventive methodology entails the use of an inert species containing plasma tuned to enhanced its'"'"' vacuum ultra violet (VUV) emissions post lithography and/or post one of the etch processes of a given feature (on an identical etch platform) to entice increased crosslinking of one or more patterning materials, thus enabling increased etch resistance and reduced LER and LEW post etching processing.
40 Citations
18 Claims
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1. A method of fabricating a semiconductor structure having reduced line edge roughness/line width roughness values, comprising:
exposing at least one preprocessed patterning material located on a substrate to vacuum ultra violet (VUV) emissions to induce crosslinking of said at least one preprocessed patterning material, said VUV emissions are generated by an inert species containing plasma. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
- 14. A semiconductor structure comprising at least one feature defined by a patterned material layer, wherein said at least one feature has a line edge roughness (LER) of 1.4 nm or less and a line width roughness (LWR) of 2.3 nm or less.
Specification