Smart linearized power amplifier and related systems and methods

• US 20090174475A1
• Filed: 05/19/2004
• Published: 07/09/2009
• Est. Priority Date: 05/20/2003
• Status: Active Grant

• Current Assignee: Ameco Technologies Hong Kong Limited
• Original Assignee: Epic Communications, Inc.
• Inventors: Yuen, Cindy, Laursen, Kirk, Chu, Duc
• Granted Patent: US 7,863,983 B2
• Time in Patent Office: Days
• US Class Current: 330/133
• CPC Class Codes: H03F 1/0216 Continuous control
• CPC Class Codes: H03F 1/3247 using feedback acting on predistortion circuits H03F1/3264 takes precedence
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/372 Noise reduction and elimination in amplifier

Abstract

A power amplifier subsystem that includes a first stage amplifier and a second stage amplifier. A first bias circuit is coupled to the first stage amplifier, and the first bias circuit has a variable impedance that increases with radio frequency (RF) power. A second bias circuit is coupled to the second stage amplifier, and the second bias circuit has impedance relatively fixed with respect to radio frequency (RF) power. According to an embodiment of the invention, the first bias circuit comprises a transistor having a collector current that increases as radio frequency (RF) power increases. The second bias circuit can have a relatively fixed impedance. A method of designing an amplifier subsystem, where transistor size and resistor values are selected to obtain the desired bias and linearity characteristics, or transistor size and resistor values are selected to operate within a selected range, and amplifier performance is adjusted by changing the bias control voltage.

Claims

1. A power amplifier subsystem, comprising:

a first stage amplifier and a second stage amplifier;

a first bias circuit coupled to the first stage amplifier, the first bias circuit having a variable impedance that increases with radio frequency (RF) power; and

a second bias circuit coupled to the second stage amplifier, the second bias circuit having impedance relatively fixed with respect to radio frequency (RF) power.

2. The power amplifier subsystem of claim 1, wherein the first bias circuit comprises a transistor having a collector current that increases as radio frequency (RF) power increases.

3. A power amplifier subsystem, comprising:

a first stage amplifier and a second stage amplifier, the first and second stage amplifiers each having an input;

a first bias circuit coupled to the input of the first stage amplifier, the first bias circuit having a plurality of transistors and having a variable impedance that increases with radio frequency (RF) power and compensates for power dependency that would occur in the first stage amplifier if fixed impedance bias were used; and

a second bias circuit coupled to the second stage amplifier.

4. The power amplifier subsystem of claim 3, wherein the second bias circuit has a relatively fixed impedance.

5. A power amplifier subsystem, comprising:

a first stage amplifier and a second stage amplifier, the first and second stage amplifiers each having an input;

a first bias circuit coupled to the input of the first stage amplifier, the first bias circuit having a first and a second transistor, wherein collector current of the first transistor increases and transconductance decreases as power input to the first stage amplifier increases; and

a second bias circuit coupled to the second stage amplifier.

6. A method of designing a power amplifier subsystem, wherein the amplifier subsystem comprises:

a first stage amplifier and a second stage amplifier, the first and second stage amplifiers each having an input;

a first bias circuit coupled to the input of the first stage amplifier, the first bias circuit having a first and a second transistor, wherein collector current of the first transistor increases as power input to the first stage amplifier increases; and

a second bias circuit coupled to the second stage amplifier; and

wherein the method comprises;

selecting transistor size and resistor values to obtain the desired bias and linearity characteristics.

7. A method of designing an amplifier subsystem, wherein the amplifier subsystem comprises:

a first stage amplifier and a second stage amplifier, the first and second stage amplifiers each having an input;

a first bias circuit coupled to the input of the first stage amplifier, the first bias circuit having a first and a second transistor, wherein collector current of the first transistor increases as power input to the first stage amplifier increases, wherein the first bias circuit has an input for bias control voltage; and

a second bias circuit coupled to the second stage amplifier; and

wherein the method includes;

selecting transistor size and resistor values to operate within a selected range; and

adjusting amplifier performance by changing the bias control voltage.

8. A power amplifier subsystem, comprising:

a first stage amplifier and a second stage amplifier, the first and second stage amplifiers each having an input;

a first bias circuit coupled to the input of the first stage amplifier, the first bias circuit including;

a first transistor having an emitter and collector,

a second transistor having an emitter and collector, and

a plurality of resistors,

and wherein the emitter of the second transistor is coupled to a resistor to ground, the base of the second transistor and the emitter of the first transistor are coupled together and coupled to a resistor to ground, and to the input of the first stage amplifier through a resistor; and

a second bias circuit coupled to the second stage amplifier.

9. The power amplifier subsystem of claim 8, wherein the collector of the first transistor is coupled to a bias control voltage.

10. The power amplifier subsystem of claim 8, wherein the collector of the first transistor is coupled to a fixed voltage supply.

11. The power amplifier of claim 8, wherein the first bias circuit has a bias control voltage, wherein the bias control voltage is coupled to the collector of the second transistor and the base of the first transistor.

12. The power amplifier of claim 11, wherein the bias control voltage is coupled to the collector of the second transistor and the base of the first transistor through a resistor.

13. The power amplifier of claim 8, wherein the first transistor comprises a silicon bipolar junction transistor (BJT).

14. The power amplifier of claim 8, wherein the first transistor comprises a gallium arsenide (GaAs) heterojunction bipolar transistor (HBT).

15. The power amplifier of claim 8, wherein the first transistor comprises a silicon germanium (SiGe) heterojunction bipolar transistor (HBT).

16. The power amplifier of claim 8, wherein the second bias circuit includes:

a first transistor having an emitter and collector,

a second transistor having an emitter and collector, and

a plurality of resistors,

and wherein the emitter of the second transistor of the second bias circuit is coupled to a resistor to ground, the base of the second transistor of the second bias circuit and the emitter of the first transistor of the second bias circuit are coupled together and coupled to a resistor to ground, and to the input of the second stage amplifier through a resistor.

17. The power amplifier of claim 8 having a first and second control voltage, wherein the first control voltage is approximately 2.6V and the second control voltage is approximately 3.0V.

18. A single monolithic power amplifier subsystem, comprising:

a substrate, and, in a single monolithic microwave integrated circuit (MMIC) chip,

a first stage amplifier and a second stage amplifier, the first and second stage amplifiers each having an input;

a first bias circuit coupled to the input of the first stage amplifier, the first bias circuit including;

a first transistor having an emitter and collector,

a second transistor having an emitter and collector, and

a plurality of resistors,

and wherein the emitter of the second transistor is coupled to a resistor to ground, the base of the second transistor and the emitter of the first transistor are coupled together and coupled to a resistor to ground, and to the input of the first stage amplifier through a resistor; and

a second bias circuit coupled to the second stage amplifier.

19. The single monolithic power amplifier subsystem of claim 18, wherein the collector of the first transistor is coupled to a bias control voltage, and the collector of the first transistor is connected to a fixed voltage supply.

20. The single monolithic power amplifier of claim 18, wherein the first bias circuit has a bias control voltage, wherein the bias control voltage is coupled to the collector of the second transistor and the base of the first transistor, and wherein the bias control voltage is coupled to the collector of the second transistor and the base of the first transistor through a resistor.

21. The single monolithic power amplifier of claim 18, wherein the first transistor comprises a heterojunction bipolar transistor (HBT).

22. The single monolithic power amplifier of claim 18, wherein the second bias circuit includes

a first transistor having an emitter and collector,

a second transistor having an emitter and collector, and

a plurality of resistors,

and wherein the emitter of the second transistor of the second bias circuit is coupled to a resistor to ground, the base of the second transistor of the second bias circuit and the emitter of the first transistor of the second bias circuit are coupled together and coupled to a resistor to ground, and to the input of the second stage amplifier through a resistor.

23. A method of designing an amplifier subsystem, wherein the amplifier subsystem comprises:

a first stage amplifier and a second stage amplifier, the first and second stage amplifiers each having an input;

a first bias circuit coupled to the input of the first stage amplifier, the first bias circuit including;

a first transistor having an emitter and collector,

a second transistor having an emitter and collector, and

a plurality of resistors,

and wherein the emitter of the second transistor is coupled to a resistor to ground, the base of the second transistor and the emitter of the first transistor are coupled together and coupled to a resistor to ground, and to the input of the first stage amplifier through a resistor; and

a second bias circuit coupled to the second stage amplifier;

wherein the method includes;

adjusting the bias control voltage to a particular level to adjust bias level; and

setting the quiescent bias level to the first stage by adjusting the sizes of the first and second transistors and resistor values for the particular bias control voltage level.