CONTACTLESS IC CARD SYSTEM

• US 20090174495A1
• Filed: 02/17/2009
• Published: 07/09/2009
• Est. Priority Date: 06/10/1998
• Status: Abandoned Application

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Arisawa, Shigeru
• Application Number:
  US12/372,448
• Publication Number:
  US 20090174495A1
• Time in Patent Office: Days
• US Class Current: 332/115
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: G06K 7/0008 General problems related to the reading of electronic memory record carriers, independent of its reading method, e.g. power transfer
• CPC Class Codes: H03C 1/08 by means of variable impedance element H03C1/28 - H03C1/34, H03C1/46 - H03C1/52, H03C1/62 take precedence
• CPC Class Codes: H03C 1/14 the element being a diode
• CPC Class Codes: H03C 1/36 by means of semiconductor device having at least three electrodes H03C1/34, H03C1/50, H03C1/52, H03C1/62 take precedence
• CPC Class Codes: H03F 2200/327 Amplitude shift keying modulation being used in an amplifying circuit
• CPC Class Codes: H03F 2203/7215 the gated amplifier being switched on or off by a switch at the input of the amplifier
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03K 7/02 Amplitude modulation, i.e. PAM
• CPC Class Codes: H04L 27/04 Modulator circuits; Transmitter circuits
• CPC Class Codes: H04L 27/06 Demodulator circuits; Receiver circuits

Abstract

In a contactless IC card system, a modulating circuit manufactured in an IC form is operable at a high power efficiency. The demodulating apparatus is configured to include: first signal output means for outputting a first output signal having a predetermined phase with respect to that of an input signal, a second signal output means for outputting a second output signal having a predetermined phase with respect to that of the input signal, gate means for gating at least the second output signal, calculation means for adding, or subtracting the first output signal and the second output signal; and control means for controlling the operation of the gate means in response to a logic level of input data.

Claims

1. A communication apparatus, comprising:

carrier signal input means for inputting a carrier signal;

first signal output means for outputting a first output signal having a first predetermined phase with respect to said carrier signal;

second signal output means for outputting a second output signal having a second predetermined phase with respect to said carrier signal;

gate means for gating at least said second output signal;

operation means for operating said first output signal and said second output signal;

transmitting means for transmitting an output signal of said operation means using an antenna; and

control means for controlling the gate means by outputting a control signal to said gate means.

2. A communication apparatus as claimed in claim 1, wherein

the first output signal has a same phase as that of the input signal;

and

the second output signal has a phase opposite to that of the input signal.

3. A communication apparatus as claimed in claim 1, wherein

the first signal output means power-amplifies the first output signal to output a power-amplified first output signal;

and

said second signal output means power-amplifies said second output signal to output a power-amplified second output signal.

4. A communication apparatus as claimed in claim 1, wherein said input signal is a sine wave signal having a single frequency.

7. A communication apparatus as claimed in claim 3, wherein

said gate means controls a stopping of the power amplifying operation by said second signal output means so as to gate said second output signal;

and

said second signal output means maintains an impedance of an output terminal at a high impedance for a time period during which the power amplifying process operation is stopped.

8. A communication apparatus as claimed in claim 3, wherein at least one of said first output signal means and said second output signal means provide its respective power-amplified output signal to a switching circuit for switching operations in response to said input signal.

9. A communication apparatus as claimed in claim 3, wherein at least said second signal output means and said gate means are tri-state buffer circuits.

5. A communication apparatus as claimed in claim 23, wherein said input signal is a rectangular wave signal having a single frequency.

6. A communication apparatus as claimed in claim 5, wherein said second signal output means outputs said second output signal having a phase opposite to that of said input signal by inverting the logic level of said input signal.