HIGH FREQUENCY RADAR ALTIMETER

• US 20090174594A1
• Filed: 03/11/2009
• Published: 07/09/2009
• Est. Priority Date: 08/07/2006
• Status: Abandoned Application

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Backes, Glen B., Thomas, Steven H., Reilly, Timothy J.
• Application Number:
  US12/401,639
• Publication Number:
  US 20090174594A1
• Time in Patent Office: Days
• US Class Current: 342/94
• CPC Class Codes: G01C 5/005 altimeters for aircraft G01C5/02, G01C5/06 take precedence
• CPC Class Codes: G01S 13/18 wherein range gates are used
• CPC Class Codes: G01S 13/882 for altimeters measuring height using barometric means G01C5/06

Abstract

In one aspect, a method of radar altimeter operation, the altimeter including a high frequency counter coupled to a processor is described. The method comprises providing a continuous wave to the high frequency counter upon receipt of a transmit pulse, counting the cycles of the continuous wave, discontinuing counting of the continuous wave cycles upon receipt of a return pulse, outputting a count from the high frequency counter to the processor, and operating the processor to convert the count to an altitude.

Claims

1. A method of track gate generation within a radar altimeter comprising:

providing a stable waveform and a first set number of cycles to a first high frequency counter;

counting upon receipt of a start pulse to the first set number of cycles of the waveform and closing a track gate at that time;

providing the stable waveform and a second set number of cycles to a second high frequency counter; and

opening the track gate when the second set number of cycles is reached.

2. A method of track gate generation according to claim 1 wherein providing a stable waveform and a first set number of cycles to a first high frequency counter comprises configuring a processor to provide the first set number of cycles to the first high frequency counter.

3. A method of track gate generation according to claim 1 wherein providing a stable waveform and a second set number of cycles to a second high frequency counter comprises configuring a processor to provide the second set number of cycles to the second high frequency counter.

4. A method of track gate generation according to claim 1 wherein providing a stable waveform to a first high frequency counter comprises configuring a phase locked loop circuit to provide the stable waveform to the first high frequency counter for counting.

5. A method of track gate generation according to claim 1 wherein providing a stable waveform to a second high frequency counter comprises configuring a phase locked loop circuit to provide the stable waveform to the second high frequency counter for counting.

6. A method of track gate generation according to claim 1 wherein providing a stable waveform to a second high frequency counter comprises configuring the first high frequency counter, upon reaching the first set number of cycles, to provide a set pulse to a memory device, and configuring the memory device to output a start pulse to an RF switch configured to pass the stable waveform to the second high frequency counter for counting.

7. A method of track gate generation according to claim 1 wherein counting upon receipt of a start pulse to the first set number of cycles of the waveform and closing a track gate at that time comprises configuring the first high frequency counter, upon reaching the first set number of cycles, to provide a set pulse to a memory device, and configuring the memory device to output a start pulse to a gate generator and a gate switch, signaling the gate generator and the gate switch to close a track/no track gate and a track gate.

8. A method of track gate generation according to claim 1 wherein opening the track gate when the second set number of cycles is reached comprises configuring the second high frequency counter to provide a reset pulse to the memory device upon reaching the second set number of cycles and configuring the memory device to signal a gate switch to open a track gate.

9. A precision track gate generator comprising;

a phase locked loop (PLL) circuit configured to provide a stable waveform to a first and a second high frequency counter;

a processor configured to provide a first set number of pulses to said first high frequency counter and a second set number of pulses to said second high frequency counter;

said first high frequency counter configured to count pulses of the waveform and signal the start of a track gate pulse upon reaching the first set number of pulses; and

said second high frequency counter configured to count pulses of the waveform and signal the end of the track gate pulse upon reaching a second set number of pulses.

10. A precision track gate generator according to claim 9 wherein said first high frequency counter is configured to provide a set pulse to a memory device upon reaching the first set number of pulses.

11. A precision track gate generator according to claim 10 wherein said memory device is configured to provide a start pulse to a radio frequency (RF) switch, said RF switch is configured to pass the stable waveform to said second high frequency counter upon receipt of the start pulse.

12. A precision track gate generator according to claim 10 wherein said memory device is configured to signal a gate switch to close a track gate.

13. A precision track gate generator according to claim 10 wherein said memory device is configured to signal a gate generator to close a track/no track gate.

14. A precision track gate generator according to claim 9 wherein said second high frequency counter is configured to provide said memory device with a reset pulse upon reaching a second set number of pulses.

15. A precision track gate generator according to claim 14 wherein said memory device is further configured to signal the gate switch to open the track gate upon receipt of the reset pulse.