DEVICE FOR READING A LOW-CONSUMPTION NON-VOLATILE MEMORY AND ITS IMPLEMENTING METHOD

• US 20090175074A1
• Filed: 12/22/2008
• Published: 07/09/2009
• Est. Priority Date: 12/21/2007
• Status: Active Grant

• Current Assignee: EM Microelectronic - Marin SA (The Swatch Group AG)
• Original Assignee: EM Microelectronic - Marin SA (The Swatch Group AG)
• Inventors: Jaeggi, Hugo, Theoduloz, Yves, Harabech, Nadia
• Granted Patent: US 7,843,737 B2
• Time in Patent Office: Days
• US Class Current: 365/185.200
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 7/08 Control thereof
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

The reading device enables a non-volatile memory consisting of a matrix of memory cells (T_M) to be read. Once the memory cells have been selected to be read in a read cycle controlled by a microprocessor unit, sense amplifiers (4) activated at the start of each cycle supply a binary data word (dx) representing the reading of the selected memory cells. The reading device also comprises time-lag means (3, M_F, T_F, C_gap) activated at the start of each read cycle. These time-lag means supply a reference signal (rd_mon) that controls the read time of the cells selected independently of the microprocessor unit. This read time is determined so that it is sufficient for reading all the valid data of the selected memory cells in each read cycle. The time-lag means mainly comprise a reference dummy cell (T_F) linked to a reference sense amplifier (3), which supplies the reference signal (rd_mon), and a time-lag capacitor (C_gap) linked to the dummy cell.

Claims

1. A device for reading a non-volatile memory, which consists of a matrix of memory cells, said device including means for addressing rows of the memory matrix to select at least one row of memory cells, means for addressing columns of the memory matrix to select columns for reading memory cells of the columns selected on a selected memory row in a read cycle controlled by a microprocessor unit, sense amplifiers, each connected to a respective memory cell for reading a column selected by the column addressing means, wherein all the sense amplifiers that are activated at the beginning of a read cycle by the microprocessor unit supply a binary data word representing the reading of the selected memory cells, comprising time-lag means activated at the beginning of each read cycle to supply a reference signal to control the read time of cells selected independently of the microprocessor unit, wherein this read time is determined to be sufficient to read all the valid data of the selected memory cells in each read cycle, wherein the time-lag means include a column of dummy reference cells that are programmed and matched to the memory cells of each column of the non-volatile memory, the column of dummy cells being connected by means of the column addressing means to a reference sense amplifier, which supplies the reference signal, and a time-lag capacitor connected to the column of dummy cells programmed to be non-conductive, which defines a parasitic capacitor combined with the time-lag capacitor having a determined capacitance to define the desired read time.

2. Reading device according to claim 1, characterised in that the reference sense amplifier supplies a reference signal, which is in a first state at the beginning of each read cycle controlled by the microprocessor unit when the time-lag capacitor connected with the parasitic capacitor linked to the dummy cell is in charge phase, and in a second state as soon as the time-lag capacitor in association with the parasitic capacitor are charged after a determined time lapse, wherein the shift from the first state to the second state of the reference signal controls the end of the read time of each read cycle.

3. The reading device according to claim 1, wherein the reference signal controls the storage in a latch register of the valid data of the selected memory cells.

4. The reading device according to claim 2, wherein the sense amplifiers are deactivated by an output signal of a logic circuit following the shift from the first state to the second state of the reference signal supplied in input from the logic circuit.

5. The reading device according to claim 4, wherein the logic circuit comprises a first D type flip-flop supplying the output signal of the logic circuit, a second D type flip-flop and a delay circuit arranged between the output of the second flip-flop controlled by the reference signal and a zero reset input of the first flip-flop controlled by a read cycle start signal supplied by a microprocessor unit, wherein the delay circuit allows the deactivation of the sense amplifiers to be delayed following the change in state of the reference signal.

6. The reading device according to claim 1, wherein the column addressing means comprises a number of multiplexers equivalent to the number of sense amplifiers, wherein each multiplexer is controlled by a binary word for addressing columns of N bits, wherein N is an integer greater than or equal to 1, and each being linked to a column number 2N in order to link one of these columns to a respective operating sense amplifier dependent on the binary word of address for reading the selected memory cells.

7. The method for implementing a device for reading a non-volatile memory according to claim 1, wherein for each read cycle controlled by a microprocessor unit it comprises the following steps:

activating each sense amplifier at the start of each read cycle by a cycle start signal supplied by the microprocessor unit, selecting a row and columns of memory cells to be read, wherein each selected column is linked to a respective sense amplifier, and activating the time-lag means,

reading the data of the selected memory cells by means of the sense amplifiers to supply a binary data word of the selected memory cells,

controlling the end of the read time in the read cycle by a reference signal supplied by the time-lag means independently of the microprocessor unit, wherein said read time is determined so that it is sufficient to read all the valid data of the selected memory cells in each read cycle.

8. The method according to claim 7, in which the time-lag means comprise a column of dummy cells that are programmed and matched to the memory cells of each column of the non-volatile memory, wherein the column of dummy cells defines a parasitic capacitor combined with a time-lag capacitor to define the desired read time, and the column of dummy cells is linked to a reference sense amplifier, which supplies the reference signal, wherein each sense amplifier is deactivated at the end of the read time on the basis of the reference signal, wherein said reference signal shifts from a first state during the read time, in which the parasitic capacitor and the time-lag capacitor are in charge phase by means of a current supplied by the reference sense amplifier, to a second state in which the capacitors are charged.

9. The method according to claim 7, wherein during the read time the reference signal controls the storage in a latch register of the valid data of the selected memory cells.

10. The method according to claim 7, wherein the sense amplifiers are deactivated by an output signal of a logic circuit following the shift from the first state to the second state of the reference signal supplied in input from the logic circuit, wherein said logic circuit has a delay circuit to delay the deactivation of the sense amplifiers following the change of state of the reference signal.

11. The method according to claim 8, wherein during the read time the reference signal controls the storage in a latch register of the valid data of the selected memory cells.