CURRENT SENSING METHOD AND APPARATUS FOR A MEMORY ARRAY
First Claim
1. In a memory array having memory cells with diode-like conduction characteristics, for at least one of two memory cell data states, each memory cell coupled between a word line and a bit line and having first and second nominal current levels in accordance with its data state when forward biased, a method of sensing the data state of a selected memory cell comprising the steps of:
- driving a selected word line to a selected word line bias voltage;
driving a selected bit line to a selected bit line bias voltage;
precharging a sense node to a precharge sense voltage;
summing, at the sense node, a selected bit line current and a reference current having a magnitude between the first and second nominal current levels;
thendeveloping a voltage on the sense node that increases to a higher voltage for one data state, and decreases to a lower voltage for the other data state, while the selected bit line remains substantially at the selected bit line bias voltage; and
comparing the sense node voltage with a sense reference voltage to determine the selected memory cell data state.
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Accused Products
Abstract
A memory array includes a sensing circuit for sensing bit line current while keeping the voltage of the selected bit line substantially unchanged. The word lines and bit lines are biased so that essentially no bias voltage is impressed across half-selected memory cells, which substantially eliminates leakage current through half-selected memory cells. The bit line current which is sensed arises largely from only the current through the selected memory cell. A noise detection line in the memory array reduces the effect of coupling from unselected word lines to the selected bit line. In a preferred embodiment, a three-dimensional memory array having a plurality of rail-stacks forming bit lines on more than one layer, includes at least one noise detection line associated with each layer of bit lines. A sensing circuit is connected to a selected bit line and to its associated noise detection line.
56 Citations
18 Claims
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1. In a memory array having memory cells with diode-like conduction characteristics, for at least one of two memory cell data states, each memory cell coupled between a word line and a bit line and having first and second nominal current levels in accordance with its data state when forward biased, a method of sensing the data state of a selected memory cell comprising the steps of:
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driving a selected word line to a selected word line bias voltage; driving a selected bit line to a selected bit line bias voltage; precharging a sense node to a precharge sense voltage; summing, at the sense node, a selected bit line current and a reference current having a magnitude between the first and second nominal current levels;
thendeveloping a voltage on the sense node that increases to a higher voltage for one data state, and decreases to a lower voltage for the other data state, while the selected bit line remains substantially at the selected bit line bias voltage; and comparing the sense node voltage with a sense reference voltage to determine the selected memory cell data state. - View Dependent Claims (2, 3, 4)
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5. In a memory array having memory cells with diode-like conduction characteristics, for at least one of two memory cell data states, each memory cell coupled between a word line and a bit line and having first and second nominal current levels in accordance with its data state when forward biased, a method of sensing the data state of a selected memory cell comprising the steps of:
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driving a selected word line from an unselected word line bias voltage to a selected word line bias voltage; driving a selected bit line from an unselected bit line bias voltage to a selected bit line bias voltage; and sensing current flow on the selected bit line while the selected bit line remains substantially at the selected bit line bias voltage to determine which of the first or second nominal current levels flows through the selected memory cell. wherein the sensing current flow step comprises; subtracting a reference current having a magnitude between the first and second nominal current levels from the bit line current, resulting in a net bit line current; and sensing whether the net bit line current is positive or negative. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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Specification