Three dimensional structure memory

• US 20090175104A1
• Filed: 03/17/2009
• Published: 07/09/2009
• Est. Priority Date: 04/04/1997
• Status: Active Grant

• Current Assignee: Elm 3DS Innovations LLC
• Original Assignee: Elm 3DS Innovations LLC
• Inventors: Leedy, Glenn J.
• Granted Patent: US 9,401,183 B2
• Time in Patent Office: Days
• US Class Current: 365/200
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/8083 Solid-solid interdiffusion
• CPC Class Codes: H01L 2224/8384 Sintering
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/02 Semiconductor bodies ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Claims

1. An apparatus comprising:

a first integrated circuit;

a second integrated circuit;

a thermal diffusion bond physically joining the first and second integrated circuits and providing a primary adhesion of the first and second integrated circuits; and

vertical interconnects, formed as part of the thermal diffusion bond, connecting circuitry of the first integrated circuit and circuitry of the second integrated circuit, wherein a plurality of interconnects are closely arrayed to form a group of interconnects.

2. The apparatus of claim 1, further comprising:

a third integrated circuit; and

a thermal diffusion bond joining the second and third integrated circuits.

3. The apparatus of claim 2, wherein the group of interconnects extends continuously between all of the first, second and third integrated circuits.

4. The apparatus of claim 2, wherein the first, second and third integrated circuits have devices formed at least primarily on a front surface thereof only, front surfaces of the first and third integrated circuits being bonded together, and a front surface of the third integrated circuit being bonded to a back surface of the second integrated circuit.

13. The apparatus of claim 2, further comprising vertical interconnects, formed as part of the bond, connecting circuitry of the second and third integrated circuits.

14. The apparatus of claim 4, wherein said active devices are formed from one of single crystal semiconductor material and polycrystalline semiconductor material.

15. The apparatus of claim 4, further comprising vertical interconnects, formed as part of the bond, connecting circuitry of the second and third integrated circuits.

24. The apparatus of claim 1, wherein the first integrated circuit and the second integrated circuit are formed with one of single crystal semiconductor material and polycrystalline semiconductor material.

25. The apparatus of claim 1, wherein one of the first and second integrated circuits are formed using a different process technology than another of the first and second integrated circuits, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.

26. The apparatus of claim 1, wherein at least one of the first and second integrated circuits comprises a microprocessor.

27. The apparatus of claim 1, further comprising at least one memory integrated circuit and at least one logic integrated circuit, wherein the at least one logic integrated circuit performs testing of the at least one memory integrated circuit.

28. The apparatus of claim 1, further comprising at least one memory integrated circuit having multiple memory locations including at least one memory location used for sparing, wherein data from the at least one memory location on the at least one memory integrated circuit is used instead of data from a defective memory location on the at least one memory integrated circuit.

29. The apparatus of claim 1, further comprising at least one memory integrated circuit and at least one logic integrated circuit, wherein the at least one logic integrated circuit performs programmable gate line address assignment with respect to the at least one memory integrated circuit.

30. The apparatus of claim 1, wherein a plurality of interior vertical interconnections traverse at least one of the integrated circuits.

31. The apparatus of claim 1, wherein continuous vertical interconnections connect circuitry of the first and second integrated circuits.

32. The apparatus of claim 1, wherein information processing is performed on data routed between circuitry on the first and second integrated circuits.

33. The apparatus of claim 1, wherein at least one integrated circuit has reconfiguration circuitry.

34. The apparatus of claim 1, further comprising at least one logic integrated circuit having logic for performing at least one of the following functions:

virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing.

35. The apparatus of claim 1, further comprising:

a memory array having a plurality of memory cells, a plurality of data lines, and a plurality of gate lines, each memory storage cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to a gate control signal on one of said gate lines;

circuitry for generating a gate control signal in response to an address, including means for mapping addresses to gate lines; and

a controller for determining that one of said memory cells is defective and for altering said mapping to eliminate references to said one of said memory cells.

36. The apparatus of claim 1, further comprising:

one or more controller integrated circuits;

one or more memory integrated circuits;

a plurality of data lines and a plurality of gate lines on each memory integrated circuit;

an array of memory cells on each memory integrated circuit, each memory cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to the selection of one of said gate lines;

a gate line selection circuit for enabling a gate line for a memory operation, said gate line selection circuit comprising programmable gates to receive address assignments for one or more of said gate lines, said address assignments for determining which of said gate lines is selected for each programmed address assignment; and

controller logic for determining that one of said array memory cells is defective and for altering, in at least one instance, said address assignments of said gate lines to eliminate references to that gate line that causes that defective memory cell to couple a data value to one of said data lines.

37. The apparatus of claim 36, wherein said controller logic tests said memory cells periodically to determine if any of said memory cells is defective and wherein said controller logic eliminates references in said address assignments to gate lines that cause said detected defective memory cells to couple data values to said data lines.

38. The apparatus of claim 36, further comprising programmable logic to prevent the use of data values from data lines when gate lines cause said detected defective memory cells to couple data values to said data lines.

39. The apparatus of claim 36, wherein said memory cells are arranged within physical space in a physical order and are arranged within an address space in a logical order, wherein said physical order of at least one memory cell is different than the logical order of that memory cell.

40. The apparatus of claim 36, wherein external testing of the controller logic together with testing by the controller logic of the memory cells achieves a functional testing of a preponderance of the memory cells.

41. The apparatus of claim 36, wherein testing by the controller logic of the memory cells substantially reduces or eliminates the need for external testing of the memory cells of the one or more memory integrated circuits.

42. The apparatus of claim 36, wherein altering said address assignments comprises preventing the use of at least one defective gate line and replacing references to memory cells addressed using said defective gate line with references to spare memory cells addressed using a spare gate line.

43. The apparatus of claim 4, wherein the first integrated circuit and the second integrated circuit are formed with one of single crystal semiconductor material and polycrystalline semiconductor material.

44. The apparatus of claim 4, wherein one of the first and second integrated circuits are formed using a different process technology than another of the first and second integrated circuits, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.

45. The apparatus of claim 4, wherein at least one of the first and second integrated circuits comprises a microprocessor.

46. The apparatus of claim 4, further comprising at least one memory integrated circuit and at least one logic integrated circuit, wherein the at least one logic integrated circuit performs testing of the at least one memory integrated circuit.

47. The apparatus of claim 4, further comprising at least one memory integrated circuit having multiple memory locations including at least one memory location used for sparing, wherein data from the at least one memory location on the at least one memory integrated circuit is used instead of data from a defective memory location on the at least one memory integrated circuit.

48. The apparatus of claim 4, further comprising at least one memory integrated circuit and at least one logic integrated circuit, wherein the at least one logic integrated circuit performs programmable gate line address assignment with respect to the at least one memory integrated circuit.

49. The apparatus of claim 4, wherein a plurality of interior vertical interconnections traverse at least one of the integrated circuits.

50. The apparatus of claim 4, wherein continuous vertical interconnections connect circuitry of the first and second integrated circuits.

51. The apparatus of claim 4, wherein information processing is performed on data routed between circuitry on the first and second integrated circuits.

52. The apparatus of claim 4, wherein at least one integrated circuit has reconfiguration circuitry.

53. The apparatus of claim 4, including at least one logic integrated circuit having logic for performing at least one of the following functions:

virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing.

54. The apparatus of claim 4, further comprising:

a memory array having a plurality of memory cells, a plurality of data lines, and a plurality of gate lines, each memory storage cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to a gate control signal on one of said gate lines;

circuitry for generating a gate control signal in response to an address, including means for mapping addresses to gate lines; and

a controller for determining that one of said memory cells is defective and for altering said mapping to eliminate references to said one of said memory cells.

55. The apparatus of claim 4, further comprising:

one or more controller integrated circuits;

one or more memory integrated circuits;

a plurality of data lines and a plurality of gate lines on each memory integrated circuit;

an array of memory cells on each memory integrated circuit, each memory cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to the selection of one of said gate lines;

a gate line selection circuit for enabling a gate line for a memory operation, said gate line selection circuit comprising programmable gates to receive address assignments for one or more of said gate lines, said address assignments for determining which of said gate lines is selected for each programmed address assignment; and

controller logic for determining that one of said array memory cells is defective and for altering, in at least one instance, said address assignments of said gate lines to eliminate references to that gate line that causes that defective memory cell to couple a data value to one of said data lines.

56. The apparatus of claim 55, wherein said controller logic tests said memory cells periodically to determine if any of said memory cells is defective and wherein said controller logic eliminates references in said address assignments to gate lines that cause said detected defective memory cells to couple data values to said data lines.

57. The apparatus of claim 55, further comprising programmable logic to prevent the use of data values from data lines when gate lines cause said detected defective memory cells to couple data values to said data lines.

58. The apparatus of claim 55, wherein said memory cells are arranged within physical space in a physical order and are arranged within an address space in a logical order, wherein said physical order of at least one memory cell is different than the logical order of that memory cell.

59. The apparatus of claim 55, wherein external testing of the controller logic together with testing by the controller of the memory cells achieves a functional testing of a preponderance of the memory cells.

60. The apparatus of claim 55, wherein testing by the controller logic of the memory cells substantially reduces or eliminates the need for external testing of the memory cells of the one or more memory integrated circuits.

61. The apparatus of claim 55, wherein altering said address assignments comprises preventing the use of at least one defective gate line and replacing references to memory cells addressed using said defective gate line with references to spare memory cells addressed using a spare gate line.

101. The apparatus of claim 1, wherein the first integrated circuit is fabricated using one process technology, and the second integrated circuit is fabricated using a different process technology.

104. The apparatus of claim 4 wherein the vertical interconnects are internal to the apparatus.

105. The apparatus of claim 1, wherein at least one of the integrated circuits has a thickness of one of 10 microns or less and 50 microns or less.

106. The apparatus of claim 1, wherein at least one of the integrated circuits is formed with a low stress dielectric, wherein the low stress dielectric is at least one of a silicon dioxide dielectric and an oxide of silicon dielectric and is caused to have a tensile stress of about 5×

10⁸ dynes/cm² or less.

107. The apparatus of claim 4, wherein at least one of the integrated circuits has a thickness of one of 10 microns or less and 50 microns or less.

108. The apparatus of claim 4, wherein at least one of the integrated circuits is formed with a low stress dielectric, wherein the low stress dielectric is at least one of a silicon dioxide dielectric and an oxide of silicon dielectric and is caused to have a tensile stress of about 5×

10⁸ dynes/cm² or less.

5. An apparatus comprising:

a first integrated circuit

a second integrated circuit and

vertical interconnects connecting circuitry of the first integrated circuit and circuitry of the second integrated circuit, wherein a plurality of interconnects are closely arrayed to form a group of interconnects.

6. The apparatus of claim 5, further comprising:

a third integrated circuit;

wherein a group of interconnects extends continuously between all of the first, second and third integrated circuits.

7. The apparatus of claim 6, wherein the first, second and third integrated circuits have devices formed at least primarily on a front surface thereof, front surfaces of the first and second integrated circuits being bonded together, and a front surface of the third integrated circuit being bonded to a back surface of the second integrated circuit.

8. The apparatus of claim 5, further comprising a circuit substrate separate from the first and second integrated circuits.

9. The apparatus of claim 8, wherein the first and second integrated circuits have devices formed at least primarily on a front surface thereof, a front surface of the second integrated circuit being bonded to a back surface of the first integrated circuit.

10. The apparatus of claim 7, wherein the first and second integrated circuits are bonded together by a thermal diffusion bond.

11. The apparatus of claim 5, wherein the first and second integrated circuits are bonded together by a thermal diffusion bond.

12. The apparatus of claim 11, wherein the interconnects are formed at least in part by the thermal diffusion bond.

16. The apparatus of claim 7, wherein said active devices are formed from one of single crystal semiconductor material and polycrystalline semiconductor material.

17. The apparatus of claim 9, wherein said active devices are formed from one of single crystal semiconductor material and polycrystalline semiconductor material.

18. An apparatus comprising:

a first integrated circuit;

a second integrated circuit;

a bond joining the first and second integrated circuits and providing a primary means of adhesion of the first and second integrated circuits; and

vertical interconnections, formed as part of the bond, connecting circuitry of the first integrated circuit and circuitry of the second integrated circuit, wherein a plurality of interconnections are closely arrayed to form a group of interconnects.

19. The apparatus of claim 18, further comprising:

a third integrated circuit; and

a bond joining the second and third integrated circuits.

20. The apparatus of claim 19, wherein the group of interconnects extends continuously between all of the first, second and third integrated circuits.

21. The apparatus of claim 20, wherein that portion, between the second and third integrated circuits, of the group of interconnects extending continuously between the first, second, and third integrated circuits, forms part of the bond between the second and third integrated circuits, and connects circuitry of the second and third integrated circuits.

22. The apparatus of claim 19, wherein at least one of the first, second and third integrated circuits have devices formed at least primarily on a front surface thereof only, front surfaces of the first and second integrated circuits being bonded together, and a front surface of the third integrated circuit being bonded to a back surface of the second integrated circuit.

23. The apparatus of claim 22, wherein the devices are formed from one of single crystal semiconductor material and polycrystalline semiconductor material.

62. The apparatus of claim 18, wherein the first integrated circuit and the second integrated circuit are formed with one of single crystal semiconductor material and polycrystalline semiconductor material.

63. The apparatus of claim 18, wherein one of the first and second integrated circuits are formed using a different process technology than another of the first and second integrated circuits, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.

64. The apparatus of claim 18, wherein at least one of the first and second integrated circuits comprises a microprocessor.

65. The apparatus of claim 18, further comprising at least one memory integrated circuit and at least one logic integrated circuit, wherein the at least one logic integrated circuit performs testing of the at least one memory integrated circuit.

66. The apparatus of claim 18, further comprising at least one memory integrated circuit having multiple memory locations including at least one memory location used for sparing, wherein data from the at least one memory location on the at least one memory integrated circuit is used instead of data from a defective memory location on the at least one memory integrated circuit.

67. The apparatus of claim 18, further comprising at least one memory integrated circuit and at least one logic integrated circuit, wherein the at least one logic integrated circuit performs programmable gate line address assignment with respect to the at least one memory integrated circuit.

68. The apparatus of claim 18, wherein a plurality of interior vertical interconnections traverse at least one of the integrated circuits.

69. The apparatus of claim 18, wherein continuous vertical interconnections connect circuitry of the first and second integrated circuits.

70. The apparatus of claim 18, wherein information processing is performed on data routed between circuitry on the first and second integrated circuits.

71. The apparatus of claim 18, wherein at least one integrated circuit has reconfiguration circuitry.

72. The apparatus of claim 18, further comprising at least one logic integrated circuit having logic for performing at least one of the following functions:

virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing.

73. The apparatus of claim 18, further comprising:

a memory array having a plurality of memory cells, a plurality of data lines, and a plurality of gate lines, each memory storage cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to a gate control signal on one of said gate lines;

circuitry for generating a gate control signal in response to an address, including means for mapping addresses to gate lines; and

a controller for determining that one of said memory cells is defective and for altering said mapping to eliminate references to said one of said memory cells.

74. The apparatus of claim 18, further comprising:

one or more controller integrated circuit;

one or more memory integrated circuit;

a plurality of data lines and a plurality of gate lines on each memory integrated circuit;

an array of memory cells on each memory integrated circuit, each memory cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to the selection of one of said gate lines;

a gate line selection circuit for enabling a gate line for a memory operation, said gate line selection circuit comprising programmable gates to receive address assignments for one or more of said gate lines, said address assignments for determining which of said gate lines is selected for each programmed address assignment; and

controller logic for determining that one of said array memory cells is defective and for altering, in at least one instance, said address assignments of said gate lines to eliminate references to that gate line that causes that defective memory cell to couple a data value to one of said data lines.

75. The apparatus of claim 74, wherein said controller logic tests said memory cells periodically to determine if any of said memory cells is defective and wherein said controller eliminates references in said address assignments to gate lines that cause said detected defective memory cells to couple data values to said data lines.

76. The apparatus of claim 74, further comprising programmable logic to prevent the use of data values from data lines when gate lines cause said detected defective memory cells to couple data values to said data lines.

77. The apparatus of claim 74, wherein said memory cells are arranged within physical space in a physical order and are arranged within an address space in a logical order, wherein said physical order of at least one memory cell is different than the logical order of that memory cell.

78. The apparatus of claim 74, wherein external testing of the controller logic together with testing by the controller logic of the memory cells achieves a functional testing of a preponderance of the memory cells.

79. The apparatus of claim 74, wherein testing by the controller logic of the memory cells substantially reduces or eliminates the need for external testing of the memory cells of the one or more memory integrated circuits.

80. The apparatus of claim 74, wherein altering said address assignments comprises preventing the use of at least one defective gate line and replacing references to memory cells addressed using said defective gate line with references to spare memory cells addressed using a spare gate line.

102. The apparatus of claim 18, wherein the first integrated circuit is fabricated using one process technology, and the second integrated circuit is fabricated using a different process technology.

109. The apparatus of claim 18, wherein at least one of the integrated circuits has a thickness of one of 10 microns or less and 50 microns or less.

110. The apparatus of claim 18, wherein at least one of the integrated circuits is formed with a low stress dielectric, wherein the low stress dielectric is at least one of a silicon dioxide dielectric and an oxide of silicon dielectric and is caused to have a tensile stress of about 5×

10⁸ dynes/cm² or less.

81. An information processing integrated circuit comprising:

a plurality of overlying integrated circuit layers having a first integrated circuit layer and a second integrated circuit layer and

a plurality of vertical interconnections interior to overlying portions of the integrated circuit for the transfer of data between at least two of the integrated circuit layers of said integrated circuit.

82. The apparatus of claim 81, wherein the first integrated circuit layer and the second integrated circuit layer are formed with one of single crystal semiconductor material and polycrystalline semiconductor material.

83. The apparatus of claim 81, wherein one of the first and second integrated circuit layers is formed using a different process technology than another of the first and second integrated circuits, the different process technology being selected from a group consisting of DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance.

84. The apparatus of claim 81, wherein at least one of the first and second integrated circuit layers comprises a microprocessor.

85. The apparatus of claim 81, further comprising at least one memory layer and at least one logic layer, wherein the at least one logic layer performs testing of the at least one memory layer.

86. The apparatus of claim 81, further comprising at least one memory layer having multiple memory locations including at least one memory location used for sparing, wherein data from the at least one memory location on the at least one memory layer is used instead of data from a defective memory location on the at least one memory layer.

87. The apparatus of claim 81, further comprising at least one memory layer and at least one logic layer, wherein the at least one logic layer performs programmable gate line address assignment with respect to the at least one memory layer.

88. The apparatus of claim 81, wherein a plurality of interior vertical interconnections traverse at least one of the integrated circuit layers.

89. The apparatus of claim 81, wherein continuous vertical interconnections connect circuitry of the first and second integrated circuit layers.

90. The apparatus of claim 81, wherein information processing is performed on data routed between circuitry on the first and second integrated circuit layers.

91. The apparatus of claim 81, wherein at least one integrated circuit layer has reconfiguration circuitry.

92. The apparatus of claim 81, further comprising at least one logic layer having logic for performing at least one of the following functions:

virtual memory management, ECC, indirect addressing, content addressing, data compression, data decompression, graphics acceleration, audio encoding, audio decoding, video encoding, video decoding, voice recognition, handwriting recognition, power management and database processing.

93. The apparatus of claim 81, further comprising:

a memory array having a plurality of memory cells, a plurality of data lines, and a plurality of gate lines, each memory storage cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to a gate control signal on one of said gate lines;

circuitry for generating a gate control signal in response to an address, including means for mapping addresses to gate lines; and

a controller for determining that one of said memory cells is defective and for altering said mapping to eliminate references to said one of said memory cells.

94. The apparatus of claim 81, further comprising:

one or more controller layers;

one or more memory layers;

a plurality of data lines and a plurality of gate lines on each memory layer;

an array of memory cells on each memory layer, each memory cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to the selection of one of said gate lines;

a gate line selection circuit for enabling a gate line for a memory operation, said gate line selection circuit comprising programmable gates to receive address assignments for one or more of said gate lines, said address assignments for determining which of said gate lines is selected for each programmed address assignment; and

controller logic for determining that one of said array memory cells is defective and for altering, in at least one instance, said address assignments of said gate lines to eliminate references to that gate line that causes that defective memory cell to couple a data value to one of said data lines.

95. The apparatus of claim 94, wherein said controller tests said memory cells periodically to determine if any of said memory cells is defective and wherein said controller eliminates references in said address assignments to gate lines that cause said detected defective memory cells to couple data values to said data lines.

96. The apparatus of claim 94, further comprising programmable logic to prevent the use of data values from data lines when gate lines cause said detected defective memory cells to couple data values to said data lines.

97. The apparatus of claim 94, wherein said memory cells are arranged within physical space in a physical order and are arranged within an address space in a logical order, wherein said physical order of at least one memory cell is different than the logical order of that memory cell.

98. The apparatus of claim 94, wherein external testing of the controller portion of the apparatus together with testing by the controller of the memory cells achieves a functional testing of a preponderance of the memory cells.

99. The apparatus of claim 94, wherein testing by the controller of the memory cells substantially reduces or eliminates the need for external testing of the memory cells of the memory circuit layers.

100. The apparatus of claim 94, wherein altering said address assignments comprises preventing the use of at least one defective gate line and replacing references to memory cells addressed using said defective gate line with references to spare memory cells addressed using a spare gate line.

103. The apparatus of claim 81, wherein the first integrated circuit is fabricated using one process technology, and the second integrated circuit is fabricated using a different process technology.

111. The apparatus of claim 81, wherein at least one of the integrated circuit layers has a thickness of one of 10 microns or less and 50 microns or less.

112. The apparatus of claim 81, wherein at least one of the integrated circuit layers is formed with a low stress dielectric, wherein the low stress dielectric is at least one of a silicon dioxide dielectric and an oxide of silicon dielectric and is caused to have a tensile stress of about 5×

10⁸ dynes/cm² or less.