CLOCK SYNCHRONIZATION CIRCUIT AND OPERATION METHOD THEREOF
First Claim
1. A semiconductor memory device having a clock synchronization circuit, the clock synchronization circuit comprising:
- a phase-locked loop configured to detect a phase/frequency difference between a feedback clock signal and a reference clock signal to generate an oscillation control voltage signal corresponding to the detected phase/frequency difference, and generate the feedback clock signal corresponding to the oscillation control voltage; and
an injection locking oscillation unit configured to set up a free running frequency in response to the oscillation control voltage signal and generate an internal clock signal which is synchronized with the reference clock signal.
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Abstract
A semiconductor memory device with a clock synchronization circuit capable of performing a desired phase/frequency locking operation, without the jitter peaking phenomenon and the pattern jitter of an oscillation control voltage signal using injection locking. The device includes a phase-locked loop that detects a phase/frequency difference between a feedback clock signal and a reference clock signal to generate an oscillation control voltage signal corresponding to the detected phase/frequency difference, and generates the feedback clock signal corresponding to the oscillation control voltage signal. An injection locking oscillation unit sets up a free running frequency in response to the oscillation control voltage signal and generates an internal clock signal which is synchronized with the reference clock signal.
54 Citations
30 Claims
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1. A semiconductor memory device having a clock synchronization circuit, the clock synchronization circuit comprising:
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a phase-locked loop configured to detect a phase/frequency difference between a feedback clock signal and a reference clock signal to generate an oscillation control voltage signal corresponding to the detected phase/frequency difference, and generate the feedback clock signal corresponding to the oscillation control voltage; and an injection locking oscillation unit configured to set up a free running frequency in response to the oscillation control voltage signal and generate an internal clock signal which is synchronized with the reference clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A clock synchronization circuit comprising:
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a phase/frequency detecting unit configured to detect a phase/frequency difference between a reference clock signal and a feedback clock signal and output a detection signal; a charge pumping unit configured to perform a charge pumping operation in response to the detection signal; a control voltage generating unit configured to generate an oscillation control voltage signal according to the charge pumping operation; a voltage controlled oscillator configured to generate the feedback clock signal according to the oscillation control voltage signal; and an injection locking oscillator configured to set up a free running frequency in response to the oscillation control voltage signal and generate an internal clock signal in synchronization with the reference clock signal. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A method for driving a clock synchronization circuit, the method, comprising:
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performing a phase/frequency locking operation between a reference clock signal and a feedback clock signal to generate an oscillation control voltage signal; and setting up a free running frequency in response to the oscillation control voltage signal and performing an injection clocking operation to generate an internal clock signal in synchronization with the reference clock signal. - View Dependent Claims (20, 21, 22, 23, 24, 25)
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26. A clock synchronization circuit, comprising:
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a phase/frequency detecting unit configured to detect a phase/frequency difference between a reference clock signal and a feedback clock signal and output a detection signal; a charge pumping unit configured to perform a charge pumping operation in response to the detection signal; a control voltage generating unit configured to generate an oscillation control voltage signal according to the charge pumping operation; a voltage controlled oscillator configured to generate internal source clock signals with a frequency corresponding to the oscillation control voltage signal; a dividing unit configured to divide the internal source clock signals to output the feedback clock; and an injection locking oscillator configured to set up a free running frequency in response to the oscillation control voltage signal and generate an internal clock signal in response to the internal source clock signals. - View Dependent Claims (27, 28, 29, 30)
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Specification