DIGITAL PHASE-LOCKED LOOP WITH GATED TIME-TO-DIGITAL CONVERTER

• US 20090175399A1
• Filed: 01/04/2008
• Published: 07/09/2009
• Est. Priority Date: 01/04/2008
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Sahota, Gurkanwal Singh, Sun, Bo, Yang, Zixiang
• Granted Patent: US 8,433,025 B2
• Time in Patent Office: Days
• US Class Current: 375/376
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop

Abstract

A digital PLL (DPLL) includes a time-to-digital converter (TDC) and a control unit. The TDC is periodically enabled for a short duration to quantize phase information and disabled for the remaining time to reduce power consumption. The TDC receives a first clock signal and a first reference signal and provides a TDC output indicative of the phase difference between the first clock signal and the first reference signal. The control unit generates an enable signal based on a main reference signal and enables and disables the TDC with the enable signal. In one design, the control unit delays the main reference signal to obtain the first reference signal and a second reference signal, generates the enable signal based on the main reference signal and the second reference signal, and gates a main clock signal with the enable signal to obtain the first clock signal for the TDC.

Claims

1. An apparatus comprising:

a time-to-digital converter (TDC) configured to receive a first clock signal and a first reference signal and to provide a TDC output indicative of a phase difference between the first clock signal and the first reference signal; and

a control unit configured to generate an enable signal based on a main reference signal and to enable and disable the TDC based on the enable signal.

2. The apparatus of claim 1, wherein the control unit is configured to generate the enable signal based solely on the main reference signal.

3. The apparatus of claim 1, wherein the control unit is configured to delay the main reference signal to obtain a second reference signal, and to generate the enable signal based on the main reference signal and the second reference signal.

4. The apparatus of claim 3, wherein the control unit is configured to delay the main reference signal by a programmable duration selected based on frequency of the first clock signal to obtain the second reference signal, and wherein the enable signal is active for the programmable duration.

5. The apparatus of claim 3, wherein the control unit comprises

a first delay unit configured to delay the main reference signal by a first duration and provide the first reference signal, and

a second delay unit configured to delay the first reference signal by a second duration and provide the second reference signal, and wherein the enable signal is active for the first and second durations.

6. The apparatus of claim 1, wherein the control unit is configured to gate a main clock signal with the enable signal to obtain the first clock signal, the main clock signal being continuous, and the first clock signal having at least one clock cycle around each leading edge of the first reference signal and being gated off for remaining time.

7. The apparatus of claim 6, further comprising:

a divider configured to divide an oscillator signal in frequency and provide the main clock signal.

8. The apparatus of claim 1, wherein the TDC comprises

a plurality of delay elements coupled in series and configured to receive the first clock signal,

a plurality of flip-flops coupled to the plurality of delay elements and configured to receive outputs of the plurality of delay elements at a data input and the first reference signal at a clock input, and

a converter configured to receive outputs of the plurality of flip-flops and provide the TDC output.

9. The apparatus of claim 1, further comprising:

a radio frequency (RF) accumulator configured to receive a main clock signal and count number of cycles of the main clock signal,

wherein the RF accumulator and the TDC are part of a digital phase-locked loop (DPLL), and wherein the RF accumulator is enabled when the DPLL is not locked and disabled after the DPLL has locked.

10. An integrated circuit comprising:

a time-to-digital converter (TDC) configured to receive a first clock signal and a first reference signal and to provide a TDC output indicative of a phase difference between the first clock signal and the first reference signal; and

a control unit configured to generate an enable signal based on a main reference signal and to enable and disable the TDC based on the enable signal.

11. The integrated circuit of claim 10, wherein the control unit is configured to delay the main reference signal to obtain a second reference signal, and to generate the enable signal based on the main reference signal and the second reference signal.

12. The integrated circuit of claim 11, wherein the control unit is configured to delay the main reference signal by a programmable duration selected based on frequency of the first clock signal to obtain the second reference signal, and wherein the enable signal is active for the programmable duration.

13. The integrated circuit of claim 11, wherein the control unit comprises

a first delay unit configured to delay the main reference signal by a first duration and provide the first reference signal, and

a second delay unit configured to delay the first reference signal by a second duration and provide the second reference signal, and wherein the enable signal is active for the first and second durations.

14. The integrated circuit of claim 10, wherein the control unit is configured to gate a main clock signal with the enable signal to obtain the first clock signal, the main clock signal being continuous, and the first clock signal having at least one clock cycle around each leading edge of the first reference signal and being gated off for remaining time.

15. A method of operating a digital phase-locked loop (DPLL), comprising:

generating an enable signal based on a main reference signal; and

performing time-to-digital conversion when enabled by the enable signal.

16. The method of claim 15, wherein the generating the enable signal comprises

delaying the main reference signal by a first duration to obtain a first reference signal,

delaying the first reference signal by a second duration to obtain a second reference signal, and

generating the enable signal based on the main reference signal and the second reference signal.

17. The method of claim 16, wherein the performing time-to-digital conversion comprises

gating a main clock signal with the enable signal to obtain a first clock signal, the first clock signal having at least one clock cycle around each leading edge of the first reference signal and being gated off for remaining time, and

determining a phase difference between the first clock signal and the first reference signal.

18. The method of claim 17, further comprising:

selecting the first duration or the second duration or both based on frequency of the main clock signal.

19. An apparatus comprising:

means for generating an enable signal based on a main reference signal; and

means for performing time-to-digital conversion when enabled by the enable signal.

20. The apparatus of claim 19, wherein the means for generating the enable signal comprises

means for delaying the main reference signal by a first duration to obtain a first reference signal,

means for delaying the first reference signal by a second duration to obtain a second reference signal, and

means for generating the enable signal based on the main reference signal and the second reference signal.

21. The apparatus of claim 20, wherein the means for performing time-to-digital conversion comprises

means for gating a main clock signal with the enable signal to obtain a first clock signal, the first clock signal having at least one clock cycle around each leading edge of the first reference signal and being gated off for remaining time, and

means for determining a phase difference between the first clock signal and the first reference signal.

22. The apparatus of claim 21, further comprising:

means for selecting the first duration or the second duration or both based on frequency of the main clock signal.

23. A wireless device comprising:

a digital phase-locked loop (DPLL) comprising

a time-to-digital converter (TDC) configured to receive a first clock signal and a first reference signal and to provide a TDC output indicative of a phase difference between the first clock signal and the first reference signal; and

a control unit configured to generate an enable signal based on a main reference signal and to enable and disable the TDC based on the enable signal.

24. The wireless device of claim 23, wherein the DPLL comprises

a radio frequency (RF) accumulator configured to receive a main clock signal and count number of cycles of the main clock signal, the RF accumulator being enabled when the DPLL is not locked and disabled after the DPLL has locked.

25. The wireless device of claim 23, wherein the DPLL comprises

a first modulation path configured to process a modulating signal and provide an input phase signal, and

a second modulation path configured to process the modulating signal and provide a scaled modulating signal, and wherein the input phase signal is applied prior to a loop filter and the scaled modulating signal is applied after the loop filter.