EXPOSURE MASK

• US 20090176073A1
• Filed: 03/13/2009
• Published: 07/09/2009
• Est. Priority Date: 08/12/2005
• Status: Abandoned Application

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Ohnuma, Hideto
• Application Number:
  US12/403,842
• Publication Number:
  US 20090176073A1
• Time in Patent Office: Days
• US Class Current: 428/195.100
• CPC Class Codes: G03F 1/28 with three or more diverse phases on the same PSM; Preparation thereof
• CPC Class Codes: G03F 1/32 Attenuating PSM [att-PSM], e.g. halftone PSM or PSM having semi-transparent phase shift portion,; Preparation thereof
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78624 the source and the drain regions being asymmetrical
• CPC Class Codes: Y10T 428/24802 Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]

Abstract

An exposure mask provided with a semi-transparent film, capable of forming a resist in which a convex portion is not formed in an end portion and the end portion has gentle shape. In an exposure mask having a first region and a second region having different phase and transmittance with respect to exposure light, the phase difference Δθ with respect to exposure light which transmits though the first region and the second region and the transmittance n of the second region with respect to exposure light are defined so as to satisfy following formula 1.

Δθ≦arccos(−√n/2)  [Formula 1]

Accordingly, a resist having regions with different thicknesses and having gentle shape in an edge can be formed. By performing a process such as etching with this resist, regions having different thicknesses can be formed in a self-aligned manner.

Claims

1. A semiconductor device manufactured using an exposure mask wherein a phase difference Δ

θ

of i-line (365 nm) which transmits through a transparent region and a semi-transparent region of the exposure mask and a transmittance n of the semi-transparent region with respect to the exposure light satisfy Formula 1.

Δ

θ

≦

arccos(−

√

n/2) 

 

[Formula 1]

2. A semiconductor device manufactured using an exposure mask wherein a phase difference Δ

θ

of i-line (365 nm) which transmits through a transparent region and a semi-transparent region of the exposure mask and a transmittance n of the semi-transparent region with respect to the exposure light satisfy Formula 2, and the transmittance n is in the range of 0.15 to 0.8.

Δ

θ

≦

arccos(−

√

n/2) 

 

[Formula 2]

3. A semiconductor device manufactured using an exposure mask, wherein the exposure mask comprising:

a light-transmitting substrate;

a semi-transparent film provided over the light-transmitting substrate; and

a light-shielding film provided over the semi-transparent film,

wherein a phase difference Δ

θ

between the semi-transparent film and the light-transmitting substrate with respect to i-line (365 nm) and a transmittance n of the semi-transparent film with respect to the i-line (365 nm) satisfy Formula 3.

Δ

θ

≦

arccos(−

√

n/2) 

 

[Formula 3]

4. The semiconductor device according to claim 3, wherein light-shielding film comprises a Cr film.

5. The semiconductor device according to claim 3, wherein an alloy containing Mo and Si, an alloy containing Cr and Si, or Cr is used as a material for the semi-transparent film.

6. The semiconductor device according to claim 3, wherein the transmittance of the semi-transparent film with respect to the i-line (365 nm) is in the range of 0.15 to 0.8.

7. A semiconductor device manufactured using an exposure mask, wherein the exposure mask comprising:

a light-transmitting substrate;

a semi-transparent film provided over the light-transmitting substrate; and

a light-shielding film provided over the semi-transparent film,

wherein a phase difference between the semi-transparent film and the light-transmitting substrate with respect to i-line (365 nm) is in the range of −

90°

to 90°

.

8. The exposure mask according to claim 7, wherein light-shielding film comprises a Cr film.

9. The exposure mask according to claim 7, wherein an alloy containing Mo and Si, an alloy containing Cr and Si, or Cr is used as a material for the semi-transparent film.

10. The exposure mask according to claim 7, wherein the transmittance of the semi-transparent film with respect to the i-line (365 nm) is in the range of 0.15 to 0.8.