MICROPROCESSOR ARCHITECTURE HAVING ALTERNATIVE MEMORY ACCESS PATHS
First Claim
1. A system comprising:
- non-sequential access memory;
a cache-access path in which block data is communicated between said non-sequential access memory and a cache memory; and
a direct-access path in which individually-addressed data is communicated to/from said non-sequential access memory.
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Accused Products
Abstract
The present invention is directed to a system and method which employ two memory access paths: 1) a cache-access path in which block data is fetched from main memory for loading to a cache, and 2) a direct-access path in which individually-addressed data is fetched from main memory. The system may comprise one or more processor cores that utilize the cache-access path for accessing data. The system may further comprise at least one heterogeneous functional unit that is operable to utilize the direct-access path for accessing data. In certain embodiments, the one or more processor cores, cache, and the at least one heterogeneous functional unit may be included on a common semiconductor die (e.g., as part of an integrated circuit). Embodiments of the present invention enable improved system performance by selectively employing the cache-access path for certain instructions while selectively employing the direct-access path for other instructions.
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Citations
42 Claims
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1. A system comprising:
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non-sequential access memory; a cache-access path in which block data is communicated between said non-sequential access memory and a cache memory; and a direct-access path in which individually-addressed data is communicated to/from said non-sequential access memory. - View Dependent Claims (2, 3, 11, 12, 13, 14)
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4. The system further comprising:
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a processor; a heterogeneous functional unit; and said cache memory. - View Dependent Claims (5, 6, 7, 8, 9, 10)
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15. A system comprising:
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non-sequential access main memory and a die comprising; cache memory; a micro-processor core operable to access data via a cache-access path in which block data is communicated between said non-sequential access main memory and said cache memory, and a heterogeneous functional unit operable to access data via a direct-access path in which individually-addressed data is communicated between said heterogeneous functional unit and said non-sequential access main memory. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22)
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23. A method comprising.
decoding, by a processor core of a system, an instruction of an application being executed; -
determining, by said processor core, whether a decoded instruction is of a first class that is to be processed using a cache-access path or is of a second class that is to be processed using a direct-access path; when determined that the decoded instruction is of said first class, accessing data for processing said instruction via said cache-access path in which block data is communicated between a non-sequential access memory of the system and a cache of said system; and when determined that the decoded instruction is of said second class, accessing data for processing said instruction via said direct-access path in which individually-addressed data is accessed in said non-sequential access memory. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34)
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35. A method comprising:
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decoding by a processor core of a system, an instruction of an application being executed; determining, by said processor core, whether the decoded instruction is of a first class or is of a second class; when determined that the decoded instruction is of said first class, processing the decoded instruction by said processor core, wherein said processor core accesses data for processing said decoded instruction via a cache-access path in which block data is fetched from a non-sequential access main memory of the system for loading to a cache of said system; and when determined that the decoded instruction is of said second class, sending the decoded instruction to a heterogeneous functional unit of the system for processing, wherein said heterogeneous functional unit accesses data for processing said decoded instruction via a direct-access path in which individually-addressed data is fetched from said non-sequential access main memory. - View Dependent Claims (36, 37, 38)
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39. A system comprising:
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means for providing full bandwidth memory access for non-sequential memory accesses; and means for providing full bandwidth memory access for sequential memory accesses. - View Dependent Claims (40, 41, 42)
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Specification