MICROPROCESSOR ARCHITECTURE HAVING ALTERNATIVE MEMORY ACCESS PATHS

• US 20090177843A1
• Filed: 01/04/2008
• Published: 07/09/2009
• Est. Priority Date: 01/04/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Convey Computer (Micron Technology, Inc.)
• Inventors: Wallach, Steven J., Brewer, Tony
• Granted Patent: US 9,710,384 B2
• Time in Patent Office: Days
• US Class Current: 711/131
• CPC Class Codes: G06F 12/0844 Multiple simultaneous or quasi-simultaneous cache accessing
• CPC Class Codes: G06F 12/0877 Cache access modes
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 2212/60 Details of cache memory
• CPC Class Codes: G06F 2212/68 Details of translation look-aside buffer [TLB]

Abstract

The present invention is directed to a system and method which employ two memory access paths: 1) a cache-access path in which block data is fetched from main memory for loading to a cache, and 2) a direct-access path in which individually-addressed data is fetched from main memory. The system may comprise one or more processor cores that utilize the cache-access path for accessing data. The system may further comprise at least one heterogeneous functional unit that is operable to utilize the direct-access path for accessing data. In certain embodiments, the one or more processor cores, cache, and the at least one heterogeneous functional unit may be included on a common semiconductor die (e.g., as part of an integrated circuit). Embodiments of the present invention enable improved system performance by selectively employing the cache-access path for certain instructions while selectively employing the direct-access path for other instructions.

Claims

1. A system comprising:

non-sequential access memory;

a cache-access path in which block data is communicated between said non-sequential access memory and a cache memory; and

a direct-access path in which individually-addressed data is communicated to/from said non-sequential access memory.

2. The system of claim 1 wherein in said cache-access path said block data is fetched from said non-sequential access memory for loading to said cache memory.

3. The system of claim 1 wherein in said cache-access path said block data is stored to said non-sequential access memory from said cache memory.

11. The system of claim 1 wherein said non-sequential access memoir comprises:

a scatter/gather memory module.

12. The system of claim 1 wherein said non-sequential access memory enables access of individually-referenced physical addresses, rather than block-oriented accesses.

13. The system of claim 1 wherein said system enables full bandwidth memory access for non-sequential memory accesses.

14. The system of claim 13 wherein said system further enables full bandwidth memory access for sequential memory accesses.

4. The system further comprising:

a processor;

a heterogeneous functional unit; and

said cache memory.

5. The system of claim 4 wherein in said direct-access path said individually-addressed data is fetched from said non-sequential access memory to said heterogeneous functional unit.

6. The system of claim 4 wherein in said direct-access path said individually-addressed data is stored to said non-sequential access memory from said heterogeneous functional unit.

7. The system of claim 4 comprising:

a die one which said processor, said heterogeneous functional unit, and said cache memory are included.

8. The system of claim 4 wherein said processor accesses data via said cache-access path;

and wherein said heterogeneous functional unit is operable to access data via said direct-access path.

9. The system of claim 4 wherein said heterogeneous functional unit comprises a dynamically-reconfigurable instruction set.

10. The system of claim 4 wherein said heterogeneous functional unit comprises a field-programmable gate array (FPGA).

15. A system comprising:

non-sequential access main memory and

a die comprising;

cache memory;

a micro-processor core operable to access data via a cache-access path in which block data is communicated between said non-sequential access main memory and said cache memory, and

a heterogeneous functional unit operable to access data via a direct-access path in which individually-addressed data is communicated between said heterogeneous functional unit and said non-sequential access main memory.

16. The system of claim 15 wherein in said cache-access path said block data is fetched from said non-sequential access main memory for loading to said cache memory.

17. The system of claim 15 wherein in said direct-access path said individually-addressed data is fetched from said non-sequential access main memory.

18. The system of claim 15 wherein said non-sequential access main memory comprises:

a scatter/gather memory module.

19. The system of claim 15 wherein said heterogeneous functional unit comprises a dynamically-reconfigurable instruction set.

20. The system of claim 15 wherein said heterogeneous functional unit comprises a field-programmable gate array (FPGA).

21. The system of claim 15 wherein said non-sequential access main memory enables access of individually-referenced physical addresses, rather than block-oriented accesses.

22. The system of claim 15 wherein said system enables full bandwidth memory access for non-sequential memory accesses.

23. A method comprising.

decoding, by a processor core of a system, an instruction of an application being executed;

determining, by said processor core, whether a decoded instruction is of a first class that is to be processed using a cache-access path or is of a second class that is to be processed using a direct-access path;

when determined that the decoded instruction is of said first class, accessing data for processing said instruction via said cache-access path in which block data is communicated between a non-sequential access memory of the system and a cache of said system; and

when determined that the decoded instruction is of said second class, accessing data for processing said instruction via said direct-access path in which individually-addressed data is accessed in said non-sequential access memory.

24. The method of claim 23 wherein when determined that the decoded instruction is of said first class, said block data is fetched from said non-sequential access memory of the system for loading to said cache of said system.

25. The method of claim 23 wherein when determined that the decoded instruction is of said first class, said block data is stored to said non-sequential access memory of the system from said cache of said system.

26. The method of claim 23 wherein when determined that the decoded instruction is of said second class, said individually-addressed data is fetched from said non-sequential access memory for loading to a heterogeneous functional unit of the system.

27. The method of claim 23 wherein when determined that the decoded instruction is of said second class, said individually-addressed data is stored to said non-sequential access memory from a heterogeneous functional unit of the system.

28. The method of claim 23 wherein said determining comprises:

determining whether the instruction is of a type that is likely to have reused data.

29. The method of claim 23 wherein said determining comprises:

determining whether the instruction is of a type that is likely to benefit from a block data fetch from said non-sequential access memory.

30. The method of claim 23 wherein said determining comprises:

determining that the instruction is an instruction of the processor core'"'"'s instruction set that indicates the instruction is of said second class.

31. The method of claim 23 further comprising:

when determined that the decoded instruction is of said second class, off-loading said instruction from said processor core to a heterogeneous functional unit.

32. The method of claim 31 wherein said heterogeneous functional unit performs said accessing data for processing said instruction via said direct-access path.

33. The method of claim 23 wherein said non-sequential access memory enables access of individually-referenced physical addresses, rather than block-oriented accesses.

34. The method of claim 23 wherein said non-sequential access memory enables full bandwidth memory access for non-sequential memory accesses.

35. A method comprising:

decoding by a processor core of a system, an instruction of an application being executed;

determining, by said processor core, whether the decoded instruction is of a first class or is of a second class;

when determined that the decoded instruction is of said first class, processing the decoded instruction by said processor core, wherein said processor core accesses data for processing said decoded instruction via a cache-access path in which block data is fetched from a non-sequential access main memory of the system for loading to a cache of said system; and

when determined that the decoded instruction is of said second class, sending the decoded instruction to a heterogeneous functional unit of the system for processing, wherein said heterogeneous functional unit accesses data for processing said decoded instruction via a direct-access path in which individually-addressed data is fetched from said non-sequential access main memory.

36. The method of claim 35 wherein said processor core, said cache, and said heterogeneous functional unit are included on a common die.

37. The method of claim 35 wherein said non-sequential access main memory enables retrieval of individually-referenced physical addresses, rather than block-oriented accesses.

38. The method of claim 35 wherein said non-sequential access main memory enables full bandwidth memory access for non-sequential memory accesses.

39. A system comprising:

means for providing full bandwidth memory access for non-sequential memory accesses; and

means for providing full bandwidth memory access for sequential memory accesses.

40. The system of claim 39 comprising:

non-sequential access main memory that enables access of individually-referenced physical addresses, rather than block-oriented accesses.

41. The system of claim 40 further comprising:

a processor;

a heterogeneous functional unit;

cache memory;

a cache-access path in which block data is fetched from said non-sequential access main memory for loading to said cache; and

a direct-access path in which individually-addressed data is fetched from said non-sequential access main memory.

42. The system of claim 41 wherein said processor, said heterogeneous functional unit, and said cache memory are included on a common die.