DYNAMIC REDUNDANCY FOR MICROPROCESSOR COMPONENTS AND CIRCUITS PLACED IN NONOPERATIONAL MODES

• US 20090177919A1
• Filed: 01/04/2008
• Published: 07/09/2009
• Est. Priority Date: 01/04/2008
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bose, Pradip, Zyuban, Victor, Shin, Jeonghee
• Application Number:
  US11/969,436
• Publication Number:
  US 20090177919A1
• Time in Patent Office: Days
• US Class Current: 714/10
• CPC Class Codes: G06F 11/2025 using centralised failover control functionality
• CPC Class Codes: G06F 11/2028 eliminating a faulty processor or activating a spare
• CPC Class Codes: G06F 11/2035 without idle spare hardware
• CPC Class Codes: G06F 11/2041 with more than one idle spare processing component
• CPC Class Codes: G06F 11/2051 in regular structures

Abstract

An apparatus for implementing dynamic redundancy for a microprocessor system includes a plurality of microprocessor components, each of which is capable of being selectively placed in a non-operational mode while one or more other of the microprocessor components remain in an operational mode, and then subsequently restored from the non-operational mode back to the operational mode, the spare microprocessor component configured to be switched from the non-operational mode to the operational mode whenever one of the plurality of the microprocessor components is placed in the non-operational mode, and wherein the spare microprocessor component is configured to be switched back to the non-operational mode whenever each of the microprocessor components are in the operational mode; and multiplexing circuitry configured to map the use of the microprocessor components and the spare microprocessor component with respect to the operational mode and the non-operational mode.

Claims

1. A method for implementing dynamic redundancy for a microprocessor system, the method comprising:

selectively placing at least one of a plurality of microprocessor components in a non-operational mode while one or more other of the microprocessor components remain in an operational mode, and then subsequently restoring the at least one of a plurality of microprocessor components from the non-operational mode back to the operational mode, wherein the operational mode comprises the performance of one or more tasks for which the microprocessor component is designed to execute with respect to the microprocessor system;

switching a spare microprocessor component from the non-operational mode to the operational mode whenever one of the plurality of the microprocessor components is placed in the non-operational mode, and wherein the spare microprocessor component is configured to be switched back to the non-operational mode whenever each of the microprocessor components are in the operational mode; and

mapping, through multiplexing circuitry, the use of the microprocessor components and the spare microprocessor component with respect to the operational mode and the non-operational mode;

wherein the non-operational mode comprises a process designed to reverse aging mechanisms of transistor devices included in the plurality of microprocessor components, the aging mechanisms including one or more of;

negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), and time dependent dielectric breakdown (TDDB).

2. The method of claim 1, wherein the plurality of microprocessor components further comprises individual memory arrays defining a set-associative cache;

and the spare microprocessor component comprises a spare memory array.

3. The method of claim 2, further comprising utilizing at least one data communication link associated with each of the memory arrays and the spare array so as to facilitate a data migration from a selected array for the non-operational mode to another array prior to placing the selected array in the non-operational mode, thereby avoiding a cache line invalidation operation for the selected array.

4. The method of claim 3, wherein the at least one data communication link comprises one of the following:

a dedicated connection from array to array; and

an existing read and write bus structure associated with the cache.

5. The method of claim 1, further comprising selecting microprocessor components to be placed in the non-operational mode based on error rates thereof while in the operational mode.