Apparatus and method for test and debug of a processor/core having advanced power management
First Claim
1. An integrated circuit apparatus, comprising:
- a plurality of processor/cores, each said processor core having an input for receiving an associated sleep-inhibit signal, each said processor/core responsive to the associated sleep-inhibit signal to decrease power consumption therein, and said processor/cores including respective in-circuit emulation facilities;
an externally accessible input; and
an interface unit coupled to said processor/cores and said externally accessible input, said interface unit configured to provide said sleep-inhibit signals to the associated processor/cores in response to said externally accessible input, said interface unit further configured to permit said in-circuit emulation facilities to be controlled from said externally accessible input.
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Abstract
An interface unit is provided in a JTAG test and debug procedure involving a plurality of processor cores. The interface unit includes a TAP unit. A switch unit is coupled to the interface unit and switch units are coupled to each of the plurality of processor/cores. When the processor/cores have advanced power management systems, a sleep inhibit signal can be applied to the processor/core state machine preventing the state machine from entering a lower power state. The parameters of the processor/core can be tested to determine when the test and debug procedures can be implemented. When the (power) parameters are to low to permit test and debug, the test and debug unit can provide a command forcing the state machine into a state for which test and debug procedures can be implemented.
11 Citations
19 Claims
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1. An integrated circuit apparatus, comprising:
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a plurality of processor/cores, each said processor core having an input for receiving an associated sleep-inhibit signal, each said processor/core responsive to the associated sleep-inhibit signal to decrease power consumption therein, and said processor/cores including respective in-circuit emulation facilities; an externally accessible input; and an interface unit coupled to said processor/cores and said externally accessible input, said interface unit configured to provide said sleep-inhibit signals to the associated processor/cores in response to said externally accessible input, said interface unit further configured to permit said in-circuit emulation facilities to be controlled from said externally accessible input. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An integrated circuit apparatus, comprising:
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a plurality of processor/cores, each said processor core having associated therewith a state machine that controls a power level in said processor/core, and said processor/cores including respective in-circuit emulation facilities; an externally accessible input; and an interface unit coupled to said state machines and said externally accessible input, said interface unit configured to permit information indicative of current states of said state machines to be accessed from said externally accessible input, and said interface unit further configured to permit said in-circuit emulation facilities to be controlled from said externally accessible input. - View Dependent Claims (11, 12, 13, 14)
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15. An integrated circuit apparatus, comprising:
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a plurality of processor/cores, each said processor core having associated therewith a state machine that controls a power level in said processor/core, and said processor/cores including respective in-circuit emulation facilities; an externally accessible input; and an interface unit coupled to said state machines and said externally accessible input, said interface unit configured to permit current states of said state machines to be changed from said externally accessible input, and said interface unit further configured to permit said in-circuit emulation facilities to be controlled from said externally accessible input. - View Dependent Claims (16, 17, 18, 19)
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Specification