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Apparatus and method for test and debug of a processor/core having advanced power management

  • US 20090177923A1
  • Filed: 01/20/2009
  • Published: 07/09/2009
  • Est. Priority Date: 04/27/2005
  • Status: Active Grant
First Claim
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1. An integrated circuit apparatus, comprising:

  • a plurality of processor/cores, each said processor core having an input for receiving an associated sleep-inhibit signal, each said processor/core responsive to the associated sleep-inhibit signal to decrease power consumption therein, and said processor/cores including respective in-circuit emulation facilities;

    an externally accessible input; and

    an interface unit coupled to said processor/cores and said externally accessible input, said interface unit configured to provide said sleep-inhibit signals to the associated processor/cores in response to said externally accessible input, said interface unit further configured to permit said in-circuit emulation facilities to be controlled from said externally accessible input.

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