Method for memory testing

• US 20090177925A1
• Filed: 01/07/2008
• Published: 07/09/2009
• Est. Priority Date: 01/07/2008
• Status: Active Grant

• Current Assignee: Inventec Corporation
• Original Assignee: Inventec Corporation
• Inventors: Chen, Chi-Yuan Chu
• Granted Patent: US 7,783,926 B2
• Time in Patent Office: Days
• US Class Current: 714/36
• CPC Class Codes: G06F 11/2284 by power-on test, e.g. power-on self test [POST]
• CPC Class Codes: G11C 2029/0401 in embedded memories
• CPC Class Codes: G11C 2029/0407 on power on
• CPC Class Codes: G11C 29/16 using microprogrammed units, e.g. state machines

Abstract

A method for memory testing implemented on an embedded system, the method comprising steps of loading a booting program when the embedded system is booted; activating a RAM of the embedded system by the booting program; duplicating the booting program itself and writing the duplicated booting program into a first section of the RAM by the booting program; downloading a testing program from an on-line source and writing the downloaded testing program into a second section of the RAM by the duplicated booting program; and enabling the downloaded testing program to check a third section the rest part of the RAM excepting the first and second sections, after the downloaded testing program is executed by the duplicated booting program.

Claims

1. A method for memory testing, which is implemented on an embedded system, the method comprising:

loading a booting program when the embedded system is booted;

activating a RAM of the embedded system by the booting program;

duplicating the booting program itself and writing the duplicated booting program into a first section of the RAM by the booting program;

downloading a testing program from an on-line source and writing the downloaded testing program into a second section of the RAM by the duplicated booting program; and

enabling the downloaded testing program to check a third section which is the rest part of the RAM excepting the first and second sections, after the downloaded testing program is executed by the duplicated booting program.

2. The method as claimed in claim 1, wherein the on-line source in the downloading step is a server that obeys Trivial File Transfer Protocol (TFTP).

3. The method as claimed in claim 2, wherein the testing program provided for testing the RAM resides in the server.

4. The method as claimed in claim 3, wherein the activating step is processed by the downloaded testing program by the steps as following:

processing a data accessing testing to a plurality of data lines of the third section in the RAM;

determining respectively whether one of the data lines thereof causes errors; and

terminating the data accessing testing and outputting an error message when one of the data lines thereof causes errors.

5. The method as claimed in claim 3, wherein the activating step is processed by the downloaded testing program by the steps as following:

processing a data accessing testing to a plurality of address lines of the third section in the RAM;

determining respectively whether one of the address lines thereof causes error; and

terminating the data accessing testing and outputting an error message when one of the data lines thereof causes errors.

6. The method as claimed in claim 3, wherein the activating step is processed by the downloaded testing program by the steps as following:

processing a test of interchangedly writing and loading data to a plurality of memory addresses of the third section in the RAM;

determining respectively whether one of the memory addresses thereof causes errors; and

terminating the test of interchangedly writing and loading data and outputting an error message when one of the data lines thereof causes errors.

7. The method as claimed in claim 3, wherein the activating step is processed by the downloaded testing program by the steps as following:

writing data respectively into a plurality of memory addresses of the third section in the RAM;

loading out the data used to be written from the memory addresses thereof after a period of time;

determining respectively whether the data loaded out from the memory addresses is the same as the one used to be written into the memory addresses thereof; and

terminating the step of writing and the step of loading out, and outputting an error message when the data loaded out from the memory addresses is not the same as the one used to be written into the memory addresses thereof.

8. The method as claimed in claim 3, wherein the activating step is processed by the downloaded testing program by the steps as following:

writing a large volume of data respectively into a plurality of memory addresses of the third section in the RAM;

determining respectively whether one of the memory addresses is unable to accept the large volume of data; and

terminating the step of writing and outputting an error message when one of the memory addresses is unable to accept the large volume of data.

9. The method as claimed in claim 3, wherein the activating step is processed by the downloaded testing program by the steps as following:

processing a data accessing testing to one of a plurality of memory addresses of the third section in the RAM randomly;

determining respectively whether one of the memory addresses thereof causes error; and

terminating the data accessing testing and outputting an error message when one of the memory addresses thereof causes errors.