Memory Initialization Time Reduction
First Claim
1. A computer system comprising:
- a processor;
a memory further comprising a first memory unit, the first memory unit further comprising more than one memory rank;
a memory controller coupled to the processor and to the memory, the memory controller coupled to the memory unit with a rank select having a rank select signal unique to the each memory rank in the memory unit, the memory controller further comprising;
a functional encoded rank select;
an initialization encoded rank select;
a multiplexer configured to select the functional encoded rank select or the initialization encoded ranks select and output an encoded rank select;
a parity generator configured to generate a parity of the value of the encoded rank select;
an initialization control configured to, during a memory initialization period;
drive the initialization encoded rank select;
cause the multiplexer to select the initialization encoded rank select; and
cause a first rank select signal for a first memory rank and a second rank select signal for a second memory rank to be active at a particular time;
the initialization control further configured, during functional reads and writes, to cause the multiplexer to select the functional encoded rank select;
andan error checking and correcting (ECC) unit that receives the parity from the parity generator and which generates ECC bits that are stored in a memory rank having an active rank select signal.
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Accused Products
Abstract
A method and apparatus to improve memory initialization in a memory of a computer system. Memory units in the memory comprise a plurality of ranks, each rank having a unique rank select. A parity generator outputs a parity bit corresponding to whether an encoded rank select has an even or odd number of “1”s. The parity bit is used by an Error Checking and Correcting (ECC) unit that generates ECC bits that are stored in a rank having an active rank select. During a first interval in a memory initialization period, ranks having an even number of “1”s in their encoded rank select are initialized in parallel. During a second interval in the memory initialization period, ranks having an odd number of “1”s in their encoded rank select are initialized in parallel.
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Citations
10 Claims
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1. A computer system comprising:
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a processor; a memory further comprising a first memory unit, the first memory unit further comprising more than one memory rank; a memory controller coupled to the processor and to the memory, the memory controller coupled to the memory unit with a rank select having a rank select signal unique to the each memory rank in the memory unit, the memory controller further comprising; a functional encoded rank select; an initialization encoded rank select; a multiplexer configured to select the functional encoded rank select or the initialization encoded ranks select and output an encoded rank select; a parity generator configured to generate a parity of the value of the encoded rank select; an initialization control configured to, during a memory initialization period; drive the initialization encoded rank select; cause the multiplexer to select the initialization encoded rank select; and cause a first rank select signal for a first memory rank and a second rank select signal for a second memory rank to be active at a particular time; the initialization control further configured, during functional reads and writes, to cause the multiplexer to select the functional encoded rank select; and an error checking and correcting (ECC) unit that receives the parity from the parity generator and which generates ECC bits that are stored in a memory rank having an active rank select signal. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of initializing multiple ranks in a memory unit of a computer, the computer having a memory controller that uses a parity of an encoded rank select in generating ECC (Error Checking and Correction) bits during writes to a memory unit having a plurality of memory ranks, the method comprising:
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selecting, during a first interval in an initialization period, a first set of more than one memory ranks in a memory unit, each memory rank in the first set having an encoded rank select having an even number of “
1”
s;writing initialization data, including ECC bits, to the first set of more than one memory ranks in the memory unit; selecting, during a second interval in the initialization period, a second set of more than one memory ranks in a memory unit, each memory rank in the second set having an encoded rank select having an odd number of “
1”
s; andwriting initialization data, including ECC bits, to the second set of more than one memory ranks in the memory unit. - View Dependent Claims (8, 9, 10)
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Specification