CODE ERROR DETECTING DEVICE, WIRELESS SYSTEM AND CODE ERROR DETECTING METHOD

• US 20090177954A1
• Filed: 06/20/2007
• Published: 07/09/2009
• Est. Priority Date: 06/20/2006
• Status: Active Grant

• Current Assignee: Panasonic Intellectual Property Corporation of America (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Murakami, Yutaka, Matsuo, Michiaki, Fujita, Suguru, Takahashi, Kazuaki, Hasako, Satoshi
• Granted Patent: US 8,406,346 B2
• Time in Patent Office: Days
• US Class Current: 714/819
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/06 using space diversity
• CPC Class Codes: H04L 1/1812 Hybrid protocols; Hybrid automatic repeat request [HARQ]
• CPC Class Codes: H04L 1/1829 Arrangements specially adapted for the receiver end
• CPC Class Codes: H04L 25/03171 Arrangements involving maximum a posteriori probability [MAP] detection
• CPC Class Codes: H04L 25/067 providing soft decisions, i.e. decisions together with an estimate of reliability H04L25/068 and H04L25/069 take precedence; sequence estimation techniques H04L25/03178
• CPC Class Codes: H04L 27/06 Demodulator circuits; Receiver circuits

Abstract

A code error detecting device that can more precisely detect a code error due to a delayed wave is disclosed. The code error detecting device includes a receiving antenna (121) for receiving a on-off keying modulated pulse and its code-reversed pulse, a pulse detector (124) for outputting detected data in accordance with the pulses, a code comparing unit (128) for comparing each code of first received data (R1) with one of second received data (R2), wherein the first and second received data are derived from the output detected data, and an error detecting unit (129) for detecting an error of each code from a comparison result (D2) indicative of a result compared in the code comparing unit (128).

Claims

1. A code error detecting apparatus comprising;

a receiving terminal that receives a first pulse signal sequence subjected to on-off keying modulation and a second pulse signal sequence inverting a code of the first pulse signal sequence;

a pulse detecting section that outputs first and second detected data based on the first pulse signal sequence and the second pulse signal sequence received at the receiving terminal;

a code comparing section that compares codes of the first and second detected data output from the pulse detecting section; and

an error detecting section that detects errors of the codes based on comparison results in the code comparing section.

2. The code error detecting apparatus according to claim 1, wherein:

the code comparing section compares the codes of the detected data based on an exclusive disjunction; and

the error detecting section decides that the codes are errors when the exclusive disjunction in the code comparing section is zero.

3. The code error detecting apparatus according to claim 1, wherein the pulse detecting section comprises:

an envelope detector that outputs envelopes of the pulse signal sequences received at the receiving terminal;

an integrator that integrates the envelopes of the pulse signal sequences; and

a comparator that compares output values of the integrator and a predetermined threshold and outputs the detected data according to comparison decision results.

4. The code error detecting apparatus according to claim 3, wherein:

the comparator carries out the comparison per threshold, every threshold having a unique value, and outputs the detected data per threshold;

the code comparing section compares the codes of the detected data per threshold; and

the error detecting section detects errors of the codes per threshold from comparison results per threshold.

5. The code error detecting apparatus according to claim 4, further comprising a threshold controlling section that carries out control to vary the thresholds until detection results in the error detecting section satisfy a predetermined condition.

6. The code error detecting apparatus according to claim 1 further comprising:

a delay profile acquiring section that acquires a delay profile of a delay estimating symbol received at the receiving terminal;

a correlation section that carries out a correlation operation of the delay profile and a code of past decoded data to acquire a first correlation value and carries out a correlation operation of the delay profile and a inverted code of the past decoded data to acquire a second correlation value; and

a deciding section that, when a code error is detected in the error detecting section, determines a code of decoded data in which the code error is detected, according to a comparison result of the first and second correlation values.

7. The code error detecting apparatus according to claim 6, wherein, when the code error is detected, the deciding section uses the code of the first detected data as the code of the decoded data when the first correlation value is smaller than the second correlation value and uses the inverted code of the second detected data as the code of the decoded data when the first correlation value is greater than the second correlation value.

9. A radio system comprising:

a receiving apparatus that builds in a code error detecting apparatus according to claim 1; and

a transmitting apparatus that carries out on-off keying modulation of a pulse signal sequence transmitted to the receiving apparatus and transmits the pulse signal sequence.

8. A code error detecting apparatus comprising:

a receiving terminal that receives a pulse signal sequence which is subjected to on-off keying modulation and which is encoded by a Manchester code such that a polarity inverts at a center of a code;

a pulse detecting section that outputs detected data inverting the polarity at the center of the code by the Manchester code, based on the pulse signal sequence received at the receiving terminal;

a delaying section that delays the detected data output to the pulse detecting section by a predetermined period;

a polarity comparator that compares polarities of the detected data output to the pulse detecting section and the detected data delayed in the delaying section; and

an error detecting section that detects errors of codes from comparison results in the polarity comparator.

10. A code error detecting method comprising:

receiving a first pulse signal sequence subjected to on-off keying modulation and a second pulse signal sequence inverting a code of the first pulse signal sequence;

outputting first and second detected data based on the received first pulse signal sequence and second pulse signal sequence;

comparing codes of the first and second detected data; and

detecting errors of the codes based on comparison results.

11. The code error detecting method according to claim 10, further comprising:

carrying out the on-off keying modulation of the first pulse signal sequence and transmitting the first pulse signal sequence; and

inverting the code of the first pulse signal sequence and transmitting the second pulse signal sequence.