ULTRASONIC FAULT DETECTION SYSTEM USING A HIGH DYNAMIC RANGE ANALOG TO DIGITAL CONVERSION SYSTEM

• US 20090178485A1
• Filed: 03/25/2009
• Published: 07/16/2009
• Est. Priority Date: 10/14/2005
• Status: Active Grant

• Current Assignee: Olympus Ndt
• Original Assignee: Olympus Ndt
• Inventors: THOMAS, Andrew
• Granted Patent: US 8,001,842 B2
• Time in Patent Office: Days
• US Class Current: 73/627
• CPC Class Codes: G01N 2291/044 Internal reflections (echoes), e.g. on walls or defects
• CPC Class Codes: G01N 2291/102 one emitter, one receiver
• CPC Class Codes: G01N 29/043 in the interior, e.g. by shear waves
• CPC Class Codes: G01N 29/262 by electronic orientation or focusing, e.g. with phased arrays phased arrays per se G10K11/34
• CPC Class Codes: G01N 29/42 by frequency filtering or by tuning to resonant frequency
• CPC Class Codes: G01N 29/44 Processing the detected response signal , e.g. electronic circuits specially adapted therefor digital signal processing per se G06F17/00
• CPC Class Codes: G01N 29/4463 Signal correction, e.g. distance amplitude correction [DAC], distance gain size [DGS], noise filtering
• CPC Class Codes: H03M 1/188 Multi-path, i.e. having a separate analogue/digital converter for each possible range

Abstract

A method and apparatus for effecting ultrasonic flaw detection of an object processes an echo signal received from the object being tested in at least three signal channels, wherein the echo signal is scaled to different degrees along each channel to increase and extend the dynamic range of an associated A/D converter system, in a manner which dispenses with the need for using numerous analog high pass and low pass filters and a variable gain amplifier. This reduces complexity and avoids performance limitations. The digital to analog converters sample the differently scaled input signal and a selection circuit selects the output of the digital output obtained from that analog to digital converter which has the highest gain, but which has not overflowed. The digital outputs are seamlessly merged to produce an output that can be displayed as a scan display which shows the location of faults.

Claims

1. An object inspection system, comprising:

a transmit and receive section to generate a test signal and to receive a responsive echo signal;

a transducer that converts the test signal to an ultrasonic signal, applies the ultrasonic signal to a target object to be tested, receives an ultrasonic echo signal and produces the echo signal for the transmit and receive section;

a signal processing circuit coupled with the transmit and receive section for receiving and processing the echo signal, the signal processing circuit including at least two signal processing channels, each channel scaling the echo signal to a different degree, and each channel having a respective analog to digital converter;

a selection circuit which selects that output of that analog to digital converter which provides the largest amplification of the echo signal without having overflowed; and

each of the signal processing channels further comprising a first and second preamplifier which respectively provide first and second outputs of the echo signal, and including clamping circuits for the preamplifiers.

2. The system of claim 1, including a respective clamping circuit for each of the preamplifiers.

3. The system of claim 1, including a respective clamping circuit for each of the preamplifiers providing a substantially constant impedance for the input of each of the preamplifiers.

4. The system of claim 1, including a respective clamping circuit limiting the input voltage to the preamplifiers and further preventing the preamplifiers from entering into saturation.

5. The system of claim 1, including a display for displaying a scan signal produced by the signal processing circuit and representative of the echo signal.

6. The system of claim 1, further comprising in at least one of the signal channels a respective frequency filter.

7. The system of claim 1, in which each of the analog digital converters has a respective clock input, the clock inputs being synchronized with one another with a phase adjustment between activating clock edges thereof to compensate for signal path delays in each channel.

8. The system of claim 1, wherein each of the analog to digital converters has a respective overflow output, and the selection circuit including a channel select logic circuit which receives the respective overflow output and selects the output of that analog to digital converter which provides the largest amplification without having overflowed.

9. The system of claim 8, further comprising an exponent generator for scaling the output of a selected analog to digital converter output and storing the same in a random access memory.

10. The system of claim 6, wherein the filters are anti-aliasing filters.

11. The system of claim 1, including a DC offset circuit which applies a digital DC offset correction at signal location located after said selection circuit.

12. The system of claim 11, wherein the DC offset circuit includes a baseline capture circuit coupled to at least one of the first, second and third analog to digital converters to produce a correction signal, and including a baseline corrector which is capable of subtracting the correction signal from an output signal derived from one of the first, second and third analog to digital converters.

13. The system of claim 7, including a FIFO circuit that enables delaying one clock input relative to another by a selectable integer number of clock cycles.

14. The system of claim 1, including an analog signal delay module effective to delay outputs derived from one or more of the preamplifiers in a manner which enables the outputs from the preamplifiers to be synchronized.

15. The system of claim 14, wherein the analog signal delay module comprises a delay line with taps, wherein a desired tap is selected by a switch to obtain a desired delay.

16. The system of claim 14, wherein the analog signal delay module comprises delay filter elements that are switchable in and out of the signal path as needed.

17. The system of claim 14, wherein the analog signal delay module comprises an adjustable variable element that is controlled by a voltage controlled component responsive to a digital to analog converter.

18. The system of claim 1, wherein the selection circuit is coupled to respective overflow signals provided by respective ones of said analog to digital converters.

19. The system of claim 1, wherein the selection circuit is coupled to a plurality of magnitude comparators which are respectively coupled to respective ones of said analog to digital converters, wherein each of said magnitude comparators is structured to compare an output of its respective analog to digital converter to a respective predetermined reference, said selection circuit being responsive to said magnitude comparators to determine, in advance, whether one or more of said analog to digital converter is tending toward an erroneous reading.

20. The system of claim 1, including a respective base line correction system associated with respective ones of one or more of said analog to digital converters, said base line correction systems being respectively coupled to a multiplexer which channels a selected one thereof for being processed.