DISPLAY SUBSTRATE

• US 20090179203A1
• Filed: 12/09/2008
• Published: 07/16/2009
• Est. Priority Date: 01/15/2008
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Park, Hong-Sick, Lee, Byeong-Jin, Lee, Je-Hun, Jeong, Chang-Oh, Bae, Yang-Ho, Youn, Joo-Ae, Kim, Byeong-Beom, Ning, Hong-Long, Yun, Pil-Sang
• Granted Patent: US 8,044,398 B2
• Time in Patent Office: Days
• US Class Current: 257/72
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/136295 Materials; Compositions; Manufacture processes
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT

Abstract

A display substrate includes an insulating substrate, a thin-film transistor (TFT), a pixel electrode, a signal line and a pad part. The insulating substrate has a display region and a peripheral region surrounding the display region. The TFT is in the display region of the insulating substrate. The pixel electrode is in the display region of the insulating substrate and electrically connected to the TFT. The signal line is on the insulating substrate and extends from the peripheral region toward the display region. The pad part is in the peripheral region and electrically connects to the signal line. The pad part is formed in a trench of the insulating substrate and includes a region that extends into the insulating substrate. Therefore, the signal line may be securely attached to the insulating substrate.

Claims

1. A display substrate comprising:

an insulating substrate having a display region and a peripheral region surrounding the display region;

a thin-film transistor (TFT) in the display region of the insulating substrate;

a pixel electrode in the display region of the insulating substrate and electrically connected to the TFT;

a signal line on the insulating substrate extending from the peripheral region toward the display region; and

a pad part in the peripheral region electrically connected to the signal line, the pad part being formed in a trench of the insulating substrate and including a region exposing the insulating substrate, the region being defined by a contour line.

2. The display substrate of claim 1, wherein the region defined by the contour line comprises a slit shape or an island shape.

3. The display substrate of claim 2, wherein the slit extends in a direction substantially parallel to the signal line.

4. The display substrate of claim 1, further comprising a guard ring formed in the peripheral region and electrically connected to the signal line, the guard ring including a region defined by a contour line to expose the insulating substrate.

5. The display substrate of claim 4, wherein the guard ring is formed from the same layer as the pad part.

6. The display substrate of claim 5, wherein the guard ring is disposed on a side opposite to the pad part with respect to the signal line.

7. The display substrate of claim 4, wherein a distance between an outer side of the guard ring and the region defined by the contour line is no more than about 200 μ

m.

8. A display substrate comprising:

a base substrate including a trench pattern formed between a first contour line and at least one second contour line formed in a region defined by the first contour line;

a first line layer in the trench pattern of the base substrate;

an insulating layer on the base substrate having the first line layer to cover the first line layer;

a second line layer on the insulating layer;

a TFT on the base substrate and electrically connected to the first line layer and the second line layer; and

a pixel electrode on the base substrate electrically connected to the TFT.

9. The display substrate of claim 8, wherein the first line layer comprises copper, silver or an alloy thereof.

10. The display substrate of claim 9, wherein the first line layer comprises:

a seed layer on an inner surface of the trench; and

a conductive layer on the seed layer.

11. The display substrate of claim 10, wherein the seed layer comprises at least one selected from the group consisting of copper (Cu), molybdenum (Mo), titanium (Ti), titanium oxide (TiO), tantalum (Ta), an oxide thereof and a nitride thereof.

12. The display substrate of claim 8, wherein the first line layer comprises a gate pad in a peripheral region of the base substrate and a gate line electrically connected to the gate pad, and

the second line layer includes a source pad in the peripheral region and a source line electrically connected to the source pad.

13. The display substrate of claim 12, wherein the first line layer is opposite to the gate pad, and further comprises a guard ring electrically connected to a plurality of gate lines.

14. The display substrate of claim 8, wherein a distance between the first contour line and the second contour line is no more than about 200 μ

m.

15. The display substrate of claim 14, wherein a depth of the trench is no more than about 5,000 Å

.

16. The display substrate of claim 14, wherein a plurality of second contour lines having a plurality of slit shapes arranged substantially in parallel with each other is formed in the first contour line defining the gate pad, and the slit shapes expose the base substrate.

17. The display substrate of claim 16, wherein a width of each of the second contours defining the slit shapes is about 20 μ

m, and a distance between adjacent second contours is about 40 μ

m.

18. The display substrate of claim 8, wherein the first line layer comprises a source pad in the peripheral region, and

the second line layer includes a gate pad in the peripheral region.

19. The display substrate of claim 18, wherein the first contour line defines a shape of the source pad, and

the second contour line is extended in a direction substantially parallel with the source line and exposes the base substrate in the source pad along the source line.

20. The display substrate of claim 19, wherein a width of each of the second contour lines is about 20 μ

m, and a distance between adjacent second contour lines is about 40 μ

m.

21. A method for constructing conductive lines in a display substrate, said method comprising:

depositing a photoresist layer on a display substrate;

illuminating said photoresist layer with a mask, said mask comprising a trench mask structure and an island mask region, said island mask region contained within said trench mask structure;

etching display substrate to create a trench structure and an island structure within said trench structure upon said display substrate; and

forming a conductive layer within said trench structure.

22. The method of claim 21 wherein forming a conductive layer within said trench structure further comprises:

forming a seed layer within said trench structure; and

forming a metal layer upon said seed layer.

23. The method of claim 21 wherein forming a conductive layer within said trench structure further comprises:

depositing a conductive layer, said depositing step comprising an ELP process; and

exhausting gases generated by said depositing step along the side of said trench structure.

24. An exposure mask comprising:

a transparent substrate;

a reticle formed on the transparent substrate, said reticle further comprising a first mask portion wherein said first mask portion comprises;

a first contour line defining a corresponding metal region on a device substrate when said device substrate is illuminated by light through said exposure mask; and

a second contour line defining a corresponding island region within metal region on a device substrate when said device substrate is illuminated by light through said exposure mask.

25. The exposure mask of claim 24 wherein said first contour region defines a corresponding metal line on said device substrate and said second contour region defines a corresponding island region that runs substantially parallel to said corresponding island region.

26. The exposure mask of claim 25 wherein said second contour region comprises a second width, said second width being less than the distance between the first contour region and second contour region.

27. A method of manufacturing an electronic device, said method comprising:

forming a film over a substrate;

forming a photoresist over the film;

performing an exposure by using an exposure mask, said exposure mask comprising;

a transparent substrate;

a reticle formed on the transparent substrate, said reticle further comprising a first mask portion wherein said first mask portion comprises;

a first contour line defining a corresponding metal region on a device substrate when said device substrate is illuminated by light through said exposure mask; and

a second contour line defining a corresponding island region within metal region on a device substrate when said device substrate is illuminated by light through said exposure mask.

28. The method of claim 27 wherein said first contour region defines a corresponding metal line on said device substrate and said second contour region defines a corresponding island region that runs substantially parallel to said corresponding island region.

29. The method of claim 28 wherein said second contour region comprises a second width, said second width being less than the distance between the first contour region and second contour region.