BI-DIRECTIONAL TRANSISTOR WITH BY-PASS PATH AND METHOD THEREFOR

• US 20090179223A1
• Filed: 03/20/2009
• Published: 07/16/2009
• Est. Priority Date: 03/06/2006
• Status: Active Grant

• Current Assignee: Francine Y. Robb, Stephen P. Robb
• Original Assignee: Francine Y. Robb, Stephen P. Robb
• Inventors: Robb, Stephen P., Robb, Francine Y.
• Granted Patent: US 7,910,409 B2
• Time in Patent Office: Days
• US Class Current: 257/121
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

In one embodiment, a transistor is formed to have a first current flow path to selectively conduct current in both directions through the transistor and to have a second current flow path to selectively conduct current in one direction.

Claims

1. A bi-directional transistor comprising:

a first MOS transistor having a body region, a first current carrying electrode, and a second current carrying electrode;

a switch configured to selectively couple the body region of the first MOS transistor to the first current carrying electrode or the second current carrying electrode of the first MOS transistor responsively to signals applied to the first current carrying electrode and the second current carrying electrode of the first MOS transistor; and

a second MOS transistor configured to selectively form a current flow path in parallel with the first MOS transistor.

2. The bi-directional transistor of claim 1 wherein the first MOS transistor is a vertical MOS power transistor.

3. The bi-directional transistor of claim 2 wherein the vertical MOS power transistor includes trench type gates.

4. The bi-directional transistor of claim 1 wherein the switch configured to selectively couple the body region of the first MOS transistor to the first current carrying electrode or the second current carrying electrode of the first MOS transistor responsively to signals applied to the first current carrying electrode and the second current carrying electrode of the first MOS transistor includes a first switch transistor having a first current carrying electrode coupled to the body region, a second current carrying electrode coupled to the second current carrying electrode of the first MOS transistor, and a control electrode coupled to the first current carrying electrode of the first MOS transistor.

5. The bi-directional transistor of claim 4 further including a second switch transistor having a first current carrying electrode coupled to the body region, a second current carrying electrode coupled to the first current carrying electrode of the first MOS transistor, and a control electrode coupled to the second current carrying electrode of the first MOS transistor.

6. The bi-directional transistor of claim 1 wherein the body region of the first MOS transistor is devoid of a direct electrical connection to the first current carrying electrode of the first MOS transistor.

7. The bi-directional transistor of claim 1 wherein the switch configured to selectively couple the body region of the first MOS transistor to the first current carrying electrode or the second current carrying electrode of the first MOS transistor includes a third MOS transistor and a fourth MOS transistor configured to selectively couple the body region to the first current carrying electrode or the second current carrying electrode of the first MOS transistor.

8. The bi-directional transistor of claim 7 wherein the third MOS transistor is a lateral MOS transistor and the fourth MOS transistor is a vertical MOS transistor.

9. The bi-directional transistor of claim 1 further including a diode coupled in series with the second MOS transistor wherein the second MOS transistor and the diode are coupled in parallel with the first MOS transistor.

10. (canceled)

11. (canceled)

12. (canceled)

13. A method of forming a bi-directional transistor comprising:

forming a first MOS transistor on a semiconductor substrate of a first conductivity type wherein the first MOS transistor is a vertical transistor formed on the semiconductor substrate;

forming a body region of the first MOS transistor on a surface of the semiconductor substrate and isolated from a first current carrying electrode region of the first MOS transistor by a first P-N junction and isolated from a second current carrying electrode region of the first MOS transistor by a second P-N junction;

forming a second MOS transistor coupled to selectively couple the body region of the first MOS transistor to the first current carrying electrode of the first MOS transistor wherein the second MOS transistor is a vertical MOS transistor formed on the semiconductor substrate; and

forming a third MOS transistor on a surface of the semiconductor substrate and coupled to form a current flow path in parallel with the first MOS transistor.

14. (canceled)

15. A method of forming a bi-directional transistor comprising:

providing a semiconductor substrate of a first conductivity type;

forming a first doped region of a second conductivity type on a surface of the semiconductor substrate as a body region of a first transistor;

forming a second doped region of the first conductivity type within the first doped region and extending a first distance into the first doped region as a first current carrying electrode region of the first transistor;

forming a third doped region of the first conductivity type extending from the second doped region a second distance into the first doped region;

forming a fourth doped region of the second conductivity type on the surface of the semiconductor substrate; and

forming a second transistor in the fourth doped region and coupling the second transistor in parallel path with the first MOS transistor.

16. The method of claim 15 further including forming a fifth doped region of the second conductivity type on the surface of the semiconductor substrate and spaced apart from the first doped region;

forming a source and a drain of a third transistor in the fifth doped region; and

coupling the third transistor electrically between the first doped region and the semiconductor substrate.

17. The method of claim 16 wherein forming the source and the drain of the third transistor in the fifth doped region includes forming a sixth doped region within the fifth doped region;

forming a seventh doped region within the fifth doped region and spaced apart from the sixth doped region;

electrically coupling the sixth doped region to the first doped region; and

coupling the seventh doped region to the semiconductor substrate.

18. The method of claim 15 further including forming a fifth doped region of the second conductivity type on the surface of the semiconductor substrate and spaced apart from the first doped region;

forming a source and a drain of a third transistor in the fifth doped region; and

coupling the third transistor electrically between the first doped region and the second doped region.

19. The method of claim 15 wherein forming the fourth doped region of the second conductivity includes coupling the fourth doped region to the first doped region.

20. The method of claim 15 wherein forming the first doped region of the second conductivity type on the surface of the semiconductor substrate as the body region of the first transistor includes forming the first transistor and the second transistor as vertical MOS transistors.