DEVICE AND DESIGN STRUCTURES FOR MEMORY CELLS IN A NON-VOLATILE RANDOM ACCESS MEMORY AND METHODS OF FABRICATING SUCH DEVICE STRUCTURES
First Claim
1. A device structure for a non-volatile random access memory formed on an insulating layer, the device structure comprising:
- a semiconductor body in contact with the insulating layer, the semiconductor body including a source, a drain, and a channel between the source and the drain;
a control gate electrode in contact with the insulating layer;
a floating gate electrode in contact with the insulating layer, the floating gate electrode disposed between the control gate electrode and the channel of the semiconductor body;
a first dielectric layer between the channel of the semiconductor body and the floating gate electrode, the first dielectric layer composed of a first dielectric material that electrically isolates the floating gate electrode from the channel; and
a second dielectric layer between the floating gate electrode and the control gate electrode, the second dielectric layer composed of a second dielectric material that electrically isolates the floating gate electrode from the control gate electrode.
2 Assignments
0 Petitions
Accused Products
Abstract
Device and design structures for memory cells in a non-volatile random access memory (NVRAM) and methods for fabricating such device structures using complementary metal-oxide-semiconductor (CMOS) processes. The device structure, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a floating gate electrode, a semiconductor body, and a control gate electrode separated from the semiconductor body by the floating gate electrode. The floating gate electrode, the control gate electrode, and the semiconductor body, which are both formed from the monocrystalline SOI layer of the SOI substrate, are respectively separated by dielectric layers. The dielectric layers may each be composed of thermal oxide layers grown on confronting sidewalls of the semiconductor body, the floating gate electrode, and the control gate electrode. An optional deposited dielectric material may fill any remaining gap between either pair of the thermal oxide layers.
-
Citations
19 Claims
-
1. A device structure for a non-volatile random access memory formed on an insulating layer, the device structure comprising:
-
a semiconductor body in contact with the insulating layer, the semiconductor body including a source, a drain, and a channel between the source and the drain; a control gate electrode in contact with the insulating layer; a floating gate electrode in contact with the insulating layer, the floating gate electrode disposed between the control gate electrode and the channel of the semiconductor body; a first dielectric layer between the channel of the semiconductor body and the floating gate electrode, the first dielectric layer composed of a first dielectric material that electrically isolates the floating gate electrode from the channel; and a second dielectric layer between the floating gate electrode and the control gate electrode, the second dielectric layer composed of a second dielectric material that electrically isolates the floating gate electrode from the control gate electrode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
-
-
12. A method of fabricating a device structure for a non-volatile random access memory from a semiconductor layer carried on an insulating layer, the method comprising:
-
forming first, second, and third semiconductor bodies from the semiconductor layer and with a juxtaposed relationship in which the second semiconductor body is disposed between the first and third semiconductor bodies; doping the first semiconductor body to form a source and a drain; forming a first dielectric layer between the first semiconductor body and the second semiconductor body; forming a second dielectric layer between the second semiconductor body and the third semiconductor body; and partially removing the second semiconductor body and the third semiconductor body to respectively define a floating gate electrode and a control gate electrode that cooperate to control carrier flow in a channel in the first semiconductor body between the source and the drain. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
-
Specification