SEMICONDUCTOR-ON-INSULATOR HIGH-VOLTAGE DEVICE STRUCTURES, METHODS OF FABRICATING SUCH DEVICE STRUCTURES, AND DESIGN STRUCTURES FOR HIGH-VOLTAGE CIRCUITS

• US 20090179267A1
• Filed: 01/11/2008
• Published: 07/16/2009
• Est. Priority Date: 01/11/2008
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Lee, Tom C., Putnam, Christopher S., Li, Junjun, Gauthier, Robert J. JR., Abou-Khalil, Michel J., Souvick, Mitra
• Granted Patent: US 7,772,651 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

High-voltage device structures, methods for fabricating such device structures using complementary metal-oxide-semiconductor (CMOS) processes, and design structures for high-voltage circuits. The planar device structure, which is formed using a semiconductor-on-insulator (SOI) substrate, includes a semiconductor body positioned between two gate electrodes. The gate electrodes and the semiconductor body may be formed from the monocrystalline SOI layer of the SOI substrate. A dielectric layer separates each of the gate electrodes from the semiconductor body. These dielectric layers are formed by defining trenches in the SOI layer and filling the trenches with a dielectric material, which may occur concurrent with a process forming device isolation regions.

Claims

1. A device structure formed on an insulating layer, the device structure comprising:

a first gate electrode;

a second gate electrode,

a semiconductor body including a source, a drain, and a channel between the source and the drain, the semiconductor body positioned laterally on the insulating layer between the first gate electrode and the second gate electrode;

a first gate dielectric layer disposed between the semiconductor body and the first gate electrode; and

a second gate dielectric layer disposed between the semiconductor body and the second gate electrode,

wherein the semiconductor body, the first gate electrode, the second gate electrode, the first gate dielectric layer, and the second gate dielectric layer each have a contacting relationship with the insulating layer.

2. The device structure of claim 1 wherein the semiconductor body contains a monocrystalline semiconductor material composed primarily of silicon, the channel of the semiconductor body is doped with a first impurity having an first conductivity type, and the source and the drain of the semiconductor body are doped with a second impurity having an second conductivity type opposite to the first conductivity type.

3. The device structure of claim 2 wherein the first gate electrode and the second gate electrode each contain the monocrystalline semiconductor material doped with a concentration of the first impurity or a concentration of the second impurity.

4. The device structure of claim 1 wherein the semiconductor body, the first gate electrode, and the second gate electrode each contain a monocrystalline semiconductor material composed primarily of silicon, the channel, the source, and the drain of the semiconductor body are doped with a first impurity having an first conductivity type, and the first gate electrode and the second gate electrode of the semiconductor body are doped with a second impurity having an second conductivity type opposite to the first conductivity type.

5. The device structure of claim 4 further comprising:

a first portion of the monocrystalline semiconductor material extending through the first gate dielectric layer to connect the semiconductor body and the first gate electrode; and

a second portion of the monocrystalline semiconductor material extending through the second gate dielectric layer to connect the semiconductor body and the second gate electrode.

6. The device structure of claim 4 further comprising:

a first transition zone in the monocrystalline semiconductor material of the semiconductor body across which a net conductivity changes from the first conductivity type of the semiconductor body to the second conductivity type of the first gate electrode; and

a second transition zone in the monocrystalline semiconductor material of the semiconductor body across which the net conductivity changes from the first conductivity type of the semiconductor body to the second conductivity type of the second gate electrode.

7. The device structure of claim 1 wherein the first gate electrode, the second gate electrode, and the semiconductor body contain a monocrystalline semiconductor material composed primarily of silicon, and the first gate dielectric layer and the second gate dielectric layer are composed of silicon dioxide.

8. The device structure of claim 1 further comprising:

a third gate dielectric layer disposed between the first gate electrode and another semiconductor body adjacent to the first gate electrode, the third gate dielectric layer having the contacting relationship with the insulating layer.

9. The device structure of claim 1 further comprising:

a third gate electrode positioned relative to the semiconductor body such that the channel of the semiconductor body is between the third gate electrode and the insulating layer; and

a third gate dielectric layer disposed between the third gate electrode and the second gate electrode.

10. The device structure of claim 1 wherein the semiconductor body, the first gate electrode, and the second gate electrode are adjacent portions of a semiconductor layer carried on the insulating layer, the first gate dielectric layer is formed in a first trench extending from a top surface of the semiconductor layer to the insulating layer, and the second gate dielectric layer is formed in a second trench extending from the top surface of the semiconductor layer to the insulating layer.

11. The device structure of claim 1 wherein the first gate dielectric layer and the second gate dielectric layer have different widths.

12. A method for fabricating a device structure using a substrate having an insulating layer and a semiconductor layer contacting the insulating layer across an interface, the method comprising:

forming a first trench that extends through the semiconductor layer to the interface so as to define a first semiconductor body and a second semiconductor body juxtaposed with the first semiconductor body;

forming a second trench that extends through the semiconductor layer to the interface so as to define a third semiconductor body juxtaposed with the first semiconductor body so that the first semiconductor body is located between the second semiconductor body and the third semiconductor body; and

filling the first trench and the second trench with portions of a dielectric material.

13. The method of claim 12 further comprising:

doping the first semiconductor body to define a source and a drain;

doping the second semiconductor body to define a first gate electrode; and

forming a first contact electrically connected with the first gate electrode.

14. The method of claim 13 further comprising:

doping the second semiconductor body to define a second gate electrode; and

forming a second contact electrically connected with the second gate electrode.

15. The method of claim 13 wherein the first semiconductor body includes a channel between the source and the drain, and further comprising:

forming a gate dielectric layer on a top surface of the first semiconductor body;

forming a second gate electrode overlying the gate dielectric layer above the channel in the first semiconductor body; and

forming a second contact electrically connected with the second gate electrode.

16. The method of claim 12 wherein the first trench and the second trench are concurrently formed, and concurrently forming the first trench and the second trench further comprises:

selecting different widths between sidewalls of the first trench and between sidewalls of the second trench.

17. The method of claim 12 further comprising:

forming a third trench that extends through the semiconductor layer to the interface to define a fourth semiconductor body juxtaposed with the second semiconductor body so that the second semiconductor body is located between the first semiconductor body and the fourth semiconductor body; and

filling the third trench with another portion of the dielectric material when the first trench and the second trench are filled.

18. The method of claim 17 wherein the first trench, the second trench, and the third trench are concurrently formed.

19. The method of claim 17 further comprising:

forming another device structure using the fourth semiconductor body that is electrically isolated from the second semiconductor body by the another portion of the dielectric material in the third trench.