DESIGN STRUCTURES FOR HIGH-VOLTAGE INTEGRATED CIRCUITS
First Claim
1. A design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
- a first gate electrode;
a second gate electrode,a semiconductor body including a source, a drain, and a channel between the source and the drain, the semiconductor body positioned laterally on the insulating layer between the first gate electrode and the second gate electrode;
a first gate dielectric layer disposed between the semiconductor body and the first gate electrode; and
a second gate dielectric layer disposed between the semiconductor body and the second gate electrode,wherein the semiconductor body, the first gate electrode, the second gate electrode, the first gate dielectric layer, and the second gate dielectric layer each have a contacting relationship with the insulating layer.
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Abstract
Design structures for high-voltage integrated circuits. The design structure, which is formed using a semiconductor-on-insulator (SOI) substrate, may include device structure with a semiconductor body positioned between first and second gate electrodes. The first and second gate electrodes and the semiconductor body may be formed from the monocrystalline SOI layer of the SOI substrate. A dielectric layer separates each of the first and second gate electrodes from the semiconductor body. These dielectric layers are formed by defining trenches in the SOI layer and filling the trenches with a dielectric material, which may occur concurrently with a process forming other device isolation regions.
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Citations
14 Claims
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1. A design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
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a first gate electrode; a second gate electrode, a semiconductor body including a source, a drain, and a channel between the source and the drain, the semiconductor body positioned laterally on the insulating layer between the first gate electrode and the second gate electrode; a first gate dielectric layer disposed between the semiconductor body and the first gate electrode; and a second gate dielectric layer disposed between the semiconductor body and the second gate electrode, wherein the semiconductor body, the first gate electrode, the second gate electrode, the first gate dielectric layer, and the second gate dielectric layer each have a contacting relationship with the insulating layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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Specification