METAL GATE STACK AND SEMICONDUCTOR GATE STACK FOR CMOS DEVICES

• US 20090179283A1
• Filed: 12/12/2007
• Published: 07/16/2009
• Est. Priority Date: 12/12/2007
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Advanced Micro Devices, Inc., International Business Machines Corporation
• Inventors: Sleight, Jeffrey W., Henson, William K., Doris, Bruce B., Adams, Charlotte D., Fisher, Philip
• Granted Patent: US 8,030,709 B2
• Time in Patent Office: Days
• US Class Current: 257/411
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A semiconductor gate stack comprising a silicon oxide based gate dielectric and a doped semiconductor material is formed on a semiconductor substrate. A high-k material metal gate electrode comprising a high-k gate dielectric and a metal gate portion is also formed on the semiconductor substrate. Oxygen-impermeable dielectric spacers are formed on the sidewalls of the semiconductor gate stack and the high-k material metal gate stack. The oxygen-impermeable dielectric spacer on the semiconductor gate stack is removed, while the oxygen impermeable dielectric spacer on the high-k material metal gate electrode is preserved. A low-k dielectric spacer is formed on the semiconductor gate stack, which provides a low parasitic capacitance for the device employing the semiconductor gate stack.

Claims

1. A semiconductor structure comprising a high-k material metal gate structure and a semiconductor gate structure,

wherein said high-k material metal gate structure includes:

a high dielectric constant (high-k) material portion having a dielectric constant greater than 8.0 and located on a semiconductor substrate;

a metal gate portion comprising a metal and vertically abutting said high-k material portion; and

an oxygen-impermeable dielectric spacer laterally abutting sidewalls of said high-k material portion and said metal gate portion;

and wherein said semiconductor gate structure includes;

a semiconductor oxide containing gate dielectric portion having a dielectric constant less than 8.0 and located directly on said semiconductor substrate;

a doped semiconductor portion comprising a doped semiconductor material and vertically abutting said gate dielectric; and

a low-k gate spacer comprising a dielectric material having a dielectric constant less than 4.0 and laterally abutting sidewalls of said semiconductor oxide containing gate dielectric portion and said doped semiconductor portion.

2. The semiconductor structure of claim 1, wherein said high-k material portion further includes a chemical oxide portion vertically abutting said high-k material portion and said semiconductor substrate and comprising an oxide of a semiconductor material of said semiconductor substrate.

3. The semiconductor structure of claim 1, wherein said oxygen-impermeable dielectric spacer has an L-shaped vertical cross-sectional area and vertically abuts said semiconductor substrate.

4. The semiconductor structure of claim 1, further comprising another low-k gate spacer abutting said oxygen-impermeable dielectric spacer.

5. The semiconductor structure of claim 1, wherein said oxygen-impermeable dielectric spacer comprises silicon nitride.

6. The semiconductor structure of claim 1, wherein said low-k gate spacer comprises silicon oxide.

7. The semiconductor structure of claim 1, wherein said low-k gate spacer comprises a low-k dielectric material having a dielectric constant less than 2.8.

8. The semiconductor structure of claim 1, wherein said high-k material portion comprises one of HfO₂, ZrO₂, La₂O₃, Al₂O₃, TiO₂, SrTiO₃, LaAlO₃, Y₂O₃, HfO_xN_y, ZrO_xN_y, La₂O_xN_y, Al₂O_xN_y, TiO_xN_y, SrTiO_xN_y, LaAlO_xN_y, Y₂O_xN_y, a silicate thereof, and an alloy thereof, wherein each value of x is independently from about 0.5 to about 3 and each value of y is independently from 0 to about 2.

9. The semiconductor structure of claim 1, wherein said metal gate portion comprises one of TiN, ZrN, HfN, VN, NbN, TaN, WN, TiAlN, TaCN, W, Ta, Ti, other conductive refractory metal nitrides, and an alloy thereof.

10. The semiconductor structure of claim 1, wherein said high-k material metal gate structure further includes a second doped semiconductor portion comprising a doped semiconductor and vertically abutting said metal gate portion.

11. The semiconductor structure of claim 10, wherein said semiconductor gate structure further includes a third doped semiconductor portion comprising said doped semiconductor and vertically abutting said doped semiconductor portion.

12. The semiconductor structure of claim 11, wherein said third doped semiconductor portion and said doped semiconductor portion comprise different materials.

13. A method of forming a semiconductor structure comprising:

forming a first gate structure and a second gate structure on a semiconductor substrate, wherein said first gate structure includes a high dielectric constant (high-k) material portion having a dielectric constant greater than 8.0, and wherein said second gate structure includes a semiconductor oxide containing gate dielectric portion having a dielectric constant less than 8.0;

forming an oxygen-impermeable dielectric layer over said first gate structure and said second gate structure; and

removing a first portion of said oxygen-impermeable dielectric layer over said second gate structure, while protecting a second portion said oxygen-impermeable dielectric layer over said first gate structure.

14. The method of claim 13, further comprising forming a low-k spacer having a dielectric constant less than 4.0 directly on sidewalls of said second gate stack and said second portion of said oxygen-impermeable dielectric layer.

15. The method of claim 14, further comprising forming another low-k spacer having a dielectric constant less than 4.0 directly on sidewalls of said oxygen-impermeable dielectric layer over said first gate structure.

16. The method of claim 14, further comprising etching said second portion of said oxygen-impermeable dielectric layer to form an oxygen-impermeable dielectric spacer.

17. The method of claim 16, wherein said oxygen-impermeable dielectric spacer comprises silicon nitride and has an L-shaped cross-sectional area.

18. The method of claim 13, wherein said first gate structure further includes a metal gate portion comprising a metal and vertically abutting said high-k material portion, and wherein said second gate structure further includes a first doped semiconductor portion comprising a doped semiconductor material and vertically abutting said semiconductor oxide containing gate dielectric portion.

19. The method of claim 18, wherein said first gate structure further includes a chemical oxide portion vertically abutting said high-k material portion and said semiconductor substrate and comprising an oxide of a semiconductor material of said semiconductor substrate.

20. The method of claim 18, further comprising:

forming a second doped semiconductor portion directly on said metal gate portion; and

forming a third doped semiconductor portion directly on said first doped semiconductor material portion, wherein said second doped semiconductor portion and said third doped semiconductor portion have an identical composition.