METAL GATE ELECTRODES FOR REPLACEMENT GATE INTEGRATION SCHEME

• US 20090179285A1
• Filed: 01/10/2008
• Published: 07/16/2009
• Est. Priority Date: 01/10/2008
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Wood, Bingxi Sun, Chang, Chorng-Ping
• Granted Patent: US 7,892,911 B2
• Time in Patent Office: Days
• US Class Current: 257/412
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

Metal gate electrodes for a replacement gate integration scheme are described. A semiconductor device includes a substrate having a dielectric layer disposed thereon. A trench is disposed in the dielectric layer. A gate dielectric layer is disposed at the bottom of the trench and above the substrate. A gate electrode has a work-function-setting layer disposed along the sidewalls of the trench and above the gate dielectric layer at the bottom of the trench. The work-function-setting layer has a thickness at the bottom of the trench greater than the thickness along the sidewalls of the trench. A pair of source and drain regions is disposed in the substrate, on either side of the gate electrode.

Claims

1. A semiconductor device, comprising:

a substrate having a dielectric layer disposed thereon;

a trench disposed in said dielectric layer;

a gate dielectric layer disposed at the bottom of said trench and above said substrate;

a gate electrode having a work-function-setting layer disposed along the sidewalls of said trench and above said gate dielectric layer at the bottom of said trench, wherein said work-function-setting layer has a thickness at the bottom of said trench greater than the thickness along the sidewalls of said trench; and

a pair of source and drain regions disposed in said substrate, on either side of said gate electrode.

2. The semiconductor device of claim 1, wherein said gate dielectric layer comprises a hafnium oxide portion above a chemical silicon dioxide portion, wherein said work-function-setting layer comprises tantalum nitride, and wherein said gate electrode further comprises a fill metal stack including a titanium nitride layer, a titanium layer, an aluminum seed layer and a top aluminum layer.

3. The semiconductor device of claim 1, wherein the portion of said work-function-setting layer disposed along the sidewalls of said trench is directly adjacent to the sidewalls of said trench.

4. The semiconductor device of claim 3, wherein said work-function-setting layer has a thickness at the bottom of said trench at least four times greater than the thickness along the sidewalls of said trench.

5. The semiconductor device of claim 1, wherein said gate dielectric layer is further disposed along the sidewalls of said trench, and wherein the portion of said work-function-setting layer disposed along the sidewalls of said trench is adjacent to said gate dielectric layer.

6. A semiconductor device, comprising:

a substrate having a dielectric layer disposed thereon;

a trench disposed in said dielectric layer;

a gate dielectric layer disposed at the bottom of said trench and above said substrate;

a gate electrode having a first work-function-setting film disposed along the sidewalls of said trench and above said gate dielectric layer at the bottom of said trench, and having a second work-function-setting film disposed above said first work-function-setting film at the bottom of said trench; and

a pair of source and drain regions disposed in said substrate, on either side of said gate electrode.

7. The semiconductor device of claim 6, wherein said second work-function-setting film is further disposed along the sidewalls of said trench, and wherein said second work-function-setting film has a thickness at the bottom of said trench greater than the thickness along the sidewalls of said trench.

8. The semiconductor device of claim 7, wherein said second work-function-setting film has a thickness at the bottom of said trench at least four times greater than the thickness along the sidewalls of said trench.

9. The semiconductor device of claim 6, wherein said second work-function-setting film is not disposed along the sidewalls of said trench.

10. The semiconductor device of claim 6, wherein the portion of said first work-function-setting film disposed along the sidewalls of said trench is directly adjacent to the sidewalls of said trench.

11. The semiconductor device of claim 6, wherein said gate dielectric layer is further disposed along the sidewalls of said trench, and wherein the portion of said first work-function-setting film disposed along the sidewalls of said trench is adjacent to said gate dielectric layer.

12. The semiconductor device of claim 6, wherein said gate dielectric layer has a thickness in the range of 1-3 nanometers and comprises a hafnium oxide portion above a chemical silicon dioxide portion, wherein said first work-function-setting film comprises an atomic layer-deposited tantalum nitride layer having a thickness in the range of 1-2 nanometers, wherein said second work-function-setting film comprises a physical vapor-deposited tantalum nitride layer having a thickness in the range of 4-6 nanometers, and wherein said gate electrode further comprises a fill metal stack having a physical vapor-deposited titanium nitride layer with a thickness approximately in the range of 7-9 nanometers above, a physical vapor-deposited titanium layer with a thickness approximately in the range of 7-9 nanometers, an aluminum seed layer with a thickness approximately in the range of 45-55 nanometers, and a top reflow-deposited aluminum layer with a thickness approximately in the range of 190-210 nanometers.

13. A method for fabricating a semiconductor device, comprising:

providing a substrate having a dielectric layer disposed thereon;

forming a trench in said dielectric layer;

providing a gate dielectric layer at the bottom of said trench and above said substrate;

forming a first work-function-setting film of a gate electrode above said gate dielectric layer at the bottom of said trench; and

forming a second work-function-setting film of said gate electrode above said first work-function-setting film at the bottom of said trench.

14. The method of claim 13, wherein forming said first work-function-setting film includes depositing said first work-function-setting film by an atomic layer deposition process, and wherein forming said second work-function-setting film includes depositing said second work-function-setting film by a physical vapor deposition process.

15. The method of claim 14, wherein said first work-function-setting film is formed to a thickness sufficiently thick to protect said gate dielectric layer during the forming of said second work-function-setting film, but sufficiently thin for said second work-function-setting film to contribute to the work-function of said gate electrode.

16. The method of claim 13, wherein said first work-function-setting film is further formed along the sidewalls of said trench, wherein said first work-function-setting layer has a thickness at the bottom of said trench approximately equal to the thickness along the sidewalls of said trench, wherein said second work-function-setting film is further formed adjacent to said work-function-setting layer along the sidewalls of said trench, and wherein said second work-function-setting layer has a thickness at the bottom of said trench greater than the thickness adjacent to said work-function-setting layer along the sidewalls of said trench.

17. The method of claim 13, wherein said first work-function-setting film is further formed along the sidewalls of said trench, and wherein said second work-function-setting film is not formed adjacent to said work-function-setting layer along the sidewalls of said trench.

18. The method of claim 13, wherein providing said gate dielectric layer includes forming said gate dielectric layer prior to forming said trench, and wherein forming said trench includes exposing said gate dielectric layer.

19. The method of claim 13, wherein providing said gate dielectric layer includes forming said gate dielectric layer after forming said trench and prior to forming said first work-function-setting film, and wherein said gate dielectric layer is further formed along the sidewalls of said trench.

20. The method of claim 13, wherein said gate dielectric layer has a thickness in the range of 1-3 nanometers and comprises a hafnium oxide portion above a chemical silicon dioxide portion, wherein said first work-function-setting film comprises an atomic layer-deposited tantalum nitride layer having a thickness in the range of 1-2 nanometers, and wherein said second work-function-setting film comprises a physical vapor-deposited tantalum nitride layer having a thickness in the range of 4-6 nanometers.