Non-invasiv, low pin count test circuits and methods utilizing emulated stress conditions

• US 20090179660A1
• Filed: 03/17/2009
• Published: 07/16/2009
• Est. Priority Date: 12/20/2001
• Status: Active Grant

• Current Assignee: Ammisetti V. Prasad, John Laurence Melanson, Murari Kejariwal, Sherry Xiaohong Wu
• Original Assignee: Ammisetti V. Prasad, John Laurence Melanson, Murari Kejariwal, Sherry Xiaohong Wu
• Inventors: Prasad, Ammisetti V., Kejariwal, Murari, Melanson, John Laurence, Wu, Sherry Xiaohong
• Granted Patent: US 7,808,263 B2
• Time in Patent Office: Days
• US Class Current: 324/750.300
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence

Abstract

An integrated circuit including at least one internal operational block, which includes test control circuitry for initiating a test mode and testing circuitry for verifying an operation of the integrated circuit under a more stringent condition in the test mode as compared to a condition in another operating mode such that proper operation of the integrated circuit is assured in the another operating mode. Pin control circuitry selectively outputs a test signal from a selected pin in the test mode indicative of the operation of the internal block, wherein the selected pin is utilized for exchanging another signal when the integrated circuit is in the another operating mode.

Claims

1-30. -30. (canceled)

31. An integrated circuit including at least one internal operational block comprising:

test control circuitry for initiating a test mode;

testing circuitry for verifying an operation of the integrated circuit under a more stringent condition in the test mode as compared to a condition in another operating mode such that proper operation of the integrated circuit is assured in the another operating mode; and

pin control circuitry for selectively outputting a test signal from a selected pin in the test mode indicative of the operation of the internal block, wherein the selected pin is utilized for exchanging another signal when the integrated circuit is in the another operating mode.

32. The integrated circuit of claim 31, comprising a feed-forward operational amplifier.

33. The integrated circuit of claim 32, wherein the internal block comprises an amplifier stage.

34. The integrated circuit of claim 32, wherein the internal block comprises a filter.

35. The integrated circuit of claim 31, wherein the test control circuitry initiates the test mode upon power-up of the integrated circuit.

36. The integrated circuit of claim 31, wherein the testing circuitry comprises:

bias current control circuitry for setting a bias current to the internal block in the test mode to emulate the more stringent operating condition; and

measurement circuitry for monitoring an operating parameter of the internal block.

37. The integrated circuit of. Claim 36, wherein the measurement circuitry monitors an output voltage of the internal block.

38. The integrated circuit of claim 31, wherein the testing circuitry is operable in the test mode to test the integrated circuit at a temperature and measure a selected operating parameter of the internal block against a more stringent limit value compared to a limit value for the operating parameter in the another operating mode to assure proper operation of the integrated circuit at another temperature in the another operating mode.

39. The integrated circuit of claim 31, wherein the testing circuitry is operable in the test mode to test the integrated circuit at a power supply voltage and measure a selected operating parameter of the internal block against a more stringent limit value compared to a limit value for the operating parameter in the another operating mode to assure proper operation of the integrated circuit at another power supply voltage in the another operating mode.

40. The integrated circuit of claim 31, wherein the testing circuitry is operable in the test mode to test a voltage offset at a selected node of the internal block against a reduced maximum voltage offset limit value compared to a maximum voltage offset limit value in the another operating mode to assure proper operations of the internal block with a larger voltage offset at the selected node in the another operating mode.

41. The integrated circuit of claim 31, wherein the testing circuitry is operable in the test mode to vary a bias current to the internal block to emulate a worst case operating condition of the internal block in the another operating mode and in response compare an operating parameter of the internal block against a limit value.