BRIDGE DESIGN FOR SD AND MMC MULTIPLEXING
First Claim
1. A method for determining direction of signal transmission in a bi-directional signal line, comprising:
- sampling data signals at two terminals, A and B;
enabling data flow from A to B when data flow from B to A is not enabled, and a logical 0 bit is sampled at A;
enabling data flow from B to A when data flow from A to B is not enabled, and a logical 0 bit is sampled at B;
disabling data flow from A to B when data flow from A to B is enabled and two successive logical 1 bits are sampled at A; and
disabling data flow from B to A when data flow from B to A is enabled and two successive logical 1 bits are sampled at B.
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Accused Products
Abstract
A method for determining direction of signal transmission in a bi-directional signal line, including sampling data signals at two terminals, A and B, enabling data flow from A to B when data flow from B to A is not enabled, and a logical 0 bit is sampled at A, enabling data flow from B to A when data flow from A to B is not enabled, and a logical 0 bit is sampled at B, disabling data flow from A to B when data flow from A to B is enabled and two successive logical 1 bits are sampled at A, and disabling data flow from B to A when data flow from B to A is enabled and two successive logical 1 bits are sampled at B. An electrical circuit is also described and claimed.
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Citations
11 Claims
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1. A method for determining direction of signal transmission in a bi-directional signal line, comprising:
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sampling data signals at two terminals, A and B; enabling data flow from A to B when data flow from B to A is not enabled, and a logical 0 bit is sampled at A; enabling data flow from B to A when data flow from A to B is not enabled, and a logical 0 bit is sampled at B; disabling data flow from A to B when data flow from A to B is enabled and two successive logical 1 bits are sampled at A; and disabling data flow from B to A when data flow from B to A is enabled and two successive logical 1 bits are sampled at B. - View Dependent Claims (2)
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3. An electrical circuit with bi-directional signal transmission, comprising:
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a bi-directional data bus for connecting two terminals, A and B; a first signal sampler for sequentially sampling a signal at terminal A; a second signal sampler for sequentially sampling a signal at terminal B; a first level shifter for driving signals on said data bus from A to B, which may be enabled or disabled; a second level shifter for driving signals on said data bus from B to A, which may be enabled or disabled; and circuitry for enabling and disabling said first and second level shifters by carrying out instructions to; enable said first level shifter when said second level shifter is not enabled, and a logical 0 bit is sampled by said first signal sampler; enable said second level shifter when said first level shifter is not enabled, and a logical 0 bit is sampled by said second signal sampler; disable said first level shifter when said first level shifter is enabled and two successive logical 1 bits are sampled by said first signal sampler; and disable said second level shifter when said second level shifter is enabled and two successive logical 1 bits are sampled by said second signal sampler. - View Dependent Claims (4, 5, 6, 7, 8)
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9. An electrical circuit with bi-directional signal transmission, comprising:
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a bi-directional data bus for connecting a terminal, A, with two terminals, B and C; a controller for selectively connecting terminal A with terminal B or with terminal C; a first signal sampler for sequentially sampling a signal at terminal A; a second signal sampler for sequentially sampling a signal at terminal B; a third signal sampler for sequentially sampling a signal at terminal C; a first level shifter for driving signals on said data bus from A to B, which may be enabled or disabled; a second level shifter for driving signals on said data bus from B to A, which may be enabled or disabled; a third level shifter for driving signals on said data bus from A to C, which may be enabled or disabled; a fourth level shifter for driving signals on said data bus from C to A, which may be enabled or disabled; and circuitry for enabling and disabling said first, second, third and fourth level shifters by carrying out instructions to; enable said first level shifter when (i) said controller selects terminal B, (ii) said second level shifter is not enabled, and (iii) a logical 0 bit is sampled by said first signal sampler; enable said second level shifter when (i) said controller selects terminal B, (ii) said first level shifter is not enabled, and (iii) a logical 0 bit is sampled by said second signal sampler; enable said third level shifter when (i) said controller selects terminal C, (ii) said fourth level shifter is not enabled, and (iii) a logical 0 bit is sampled by said third signal sampler; enable said fourth level shifter when (i) said controller selects terminal C, (ii) said third level shifter is not enabled, and (iii) a logical 0 bit is sampled by said fourth signal sampler; disable said first level shifter when said first level shifter is enabled and two successive logical 1 bits are sampled by said first signal sampler; disable said second level shifter when said second level shifter is enabled and two successive logical 1 bits are sampled by said second signal sampler; disable said third level shifter when said third level shifter is enabled and two successive logical 1 bits are sampled by said third signal sampler; and disable said fourth level shifter when said fourth level shifter is enabled and two successive logical 1 bits are sampled by said fourth signal sampler. - View Dependent Claims (10, 11)
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Specification