DISPLAY SUBSTRATE HAVING QUANTUM WELL FOR IMPROVED ELECTRON MOBILITY AND DISPLAY DEVICE INCLUDING THE SAME

• US 20090180045A1
• Filed: 01/13/2009
• Published: 07/16/2009
• Est. Priority Date: 01/15/2008
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Choi, Jae-Ho, Oh, Hwa-Yeul, Yang, Sung-Hoon, Choi, Yong-Mo, Yoon, Kap-Soo, Kim, Sung-Ryul
• Granted Patent: US 8,319,905 B2
• Time in Patent Office: Days
• US Class Current: 349/43
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2202/108 quantum wells
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

Provided are a display substrate and a display device including the same. The display substrate includes: gate wiring; a first semiconductor pattern formed on the gate wiring and having a first energy bandgap; a second semiconductor pattern formed on the first semiconductor pattern and having a second energy bandgap which is greater than the first energy bandgap; data wiring formed on the first semiconductor pattern; and a pixel electrode electrically connected to the data wiring. Because the second energy bandgap is larger than the first energy bandgap, a quantum well is formed in the first semiconductor pattern, enhancing electron mobility therein.

Claims

1. A display substrate comprising:

gate wiring;

a first semiconductor pattern formed on the gate wiring and having a first energy bandgap;

a second semiconductor pattern formed on the first semiconductor pattern and having a second energy bandgap which is greater than the first energy bandgap;

data wiring formed on the first semiconductor pattern; and

a pixel electrode electrically connected to the data wiring.

2. The display substrate of claim 1, wherein the second semiconductor pattern is disposed under the data wiring and forms an ohmic contact with the data wiring.

3. The display substrate of claim 1, wherein the second semiconductor pattern comprises an oxide.

4. The display substrate of claim 3, wherein the second semiconductor pattern comprises O and at least one of Ga, In, Zn, Sn, Co, Ti and Mg.

5. The display substrate of claim 1, wherein the first semiconductor pattern comprises amorphous silicon.

6. The display substrate of claim 1, further comprising a third semiconductor pattern formed between the gate wiring and the first semiconductor pattern and having a third energy bandgap which is greater than the first energy bandgap, wherein a quantum well is formed in the first semiconductor pattern.

7. The display substrate of claim 1, further comprising a gate insulating film formed between the gate wiring and the first semiconductor pattern, wherein a quantum well is formed in the first semiconductor pattern.

8. The display substrate of claim 1, further comprising an ohmic contact layer disposed on the first semiconductor pattern and forming an ohmic contact with the data wiring.

9. The display substrate of claim 1, wherein a thickness of the first semiconductor pattern is approximately 200 Å

or less.

10. A display substrate including a thin film transistor comprising:

a gate electrode;

a first semiconductor pattern formed on the gate electrode and comprising amorphous silicon;

a second semiconductor pattern formed on the first semiconductor pattern and comprising an oxide;

a source electrode formed on the second semiconductor pattern; and

a drain electrode formed on the second semiconductor pattern and separated from the source electrode.

11. The display substrate of claim 10, wherein the second semiconductor pattern forms an ohmic contact with each of the source electrode and the drain electrode.

12. The display substrate of claim 10, wherein the first semiconductor pattern has a first energy bandgap, and the second semiconductor pattern has a second energy bandgap which is greater than the first energy bandgap.

13. The display substrate of claim 10, further comprising a gate insulating film formed between the gate wiring and the first semiconductor pattern, wherein a quantum well is formed in the first semiconductor pattern.

14. The display substrate of claim 10, wherein the second semiconductor pattern comprises O and at least one of Ga, In, Zn, Sn, Co, Ti and Mg.

15. The display substrate of claim 10, wherein a thickness of the first semiconductor pattern is approximately 200 Å

or less.

16. A display device comprising:

a first display substrate;

a second display substrate facing the first display substrate; and

a liquid crystal layer interposed between the first display substrate and the second display substrate,

wherein the first display substrate comprises;

gate wiring;

a first semiconductor pattern formed on the gate wiring and having a first energy bandgap;

a second semiconductor pattern formed on the first semiconductor pattern and having a second energy bandgap which is greater than the first energy bandgap;

data wiring formed on the first semiconductor pattern; and

a pixel electrode electrically connected to the data wiring.

17. The display device of claim 16, wherein the second semiconductor pattern is disposed under the data wiring and forms an ohmic contact with the data wiring.

18. The display device of claim 16, wherein the second semiconductor pattern comprises an oxide.

19. The display device of claim 18, wherein the second semiconductor pattern comprises O and at least one of Ga, In, Zn, Sn, Co, Ti and Mg.

20. The display device of claim 16, wherein the first semiconductor pattern comprises amorphous silicon.

21. The display device of claim 16, further comprising a third semiconductor pattern formed between the gate wiring and the first semiconductor pattern and having a third energy bandgap which is greater than the first energy bandgap, wherein a quantum well is formed in the first semiconductor pattern.

22. The display device of claim 16, wherein a thickness of the first semiconductor pattern is approximately 200 Å

or less.