STEPWISE CAPACITOR STRUCTURE, FABRICATION METHOD THEREOF AND SUBSTRATE EMPLOYING THE SAME

• US 20090180236A1
• Filed: 03/25/2009
• Published: 07/16/2009
• Est. Priority Date: 11/21/2007
• Status: Active Grant

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Lee, Min-Lin, Lai, Shinn-Juh, Wu, Shih-Hsien, Liu, Shur-Fen
• Granted Patent: US 8,227,894 B2
• Time in Patent Office: Days
• US Class Current: 361/301.400
• CPC Class Codes: H01G 4/012 Form of non-self-supporting electrodes
• CPC Class Codes: H01G 4/232 electrically connecting two or more layers of a stacked or rolled capacitor
• CPC Class Codes: H01G 4/30 Stacked capacitors H01G4/33 takes precedence
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A stepwise capacitor structure includes at least one stepwise conductive layer. The stepwise capacitor represents a feature of multiple capacitors. When currents flow through the stepwise capacitor, different current paths are presented in between an upper conductor and a bottom conductor of the stepwise capacitor in response to different current frequency; different inductor is induced in each path and decoupled by a stepwise capacitor structure as disclosed herein.

Claims

1. A stepwise capacitor comprising:

an upper conductive layer, a middle dielectric layer, and a lower conductive layer, wherein at least one of the two conductive layers having a stepwise structure.

2. The stepwise capacitor according to claim 1, wherein said lower conductive layer having said stepwise structure.

3. The stepwise capacitor according to claim 2 comprising:

a first step having a first upper surface; and

a second step having a second upper surface;

wherein the second upper surface being higher than the first upper surface.

4. The stepwise capacitor according to claim 3, wherein the second step is disposed on the first step.

5. The stepwise capacitor according to claim 4, wherein more than one of the second step being disposed next to each other at a distance on the first step.

6. The stepwise capacitor according to claim 4 further comprising:

a third step having a third upper surface, being disposed on the first upper surface and adjacent to the second step;

wherein the third upper surface is higher than the second upper surface.

7. The stepwise capacitor according to claim 6, wherein the third step is disposed next to the second step.

8. The stepwise capacitor according to claim 4 further comprising:

a third step disposed on the upper surface of the second step.

9. The stepwise capacitor according to claim 3, wherein the upper conductive layer having a cross section in a shape of inverse stepwise structure.

10. The stepwise capacitor according to claim 9, wherein the inverse stepwise structure comprising:

a first inverse step having a first lower surface; and

a second inverse step having a second lower surface;

wherein the second lower surface being lower than the first lower surface.

11. The stepwise capacitor according to claim 10, wherein the second lower surface is aligned to the second upper surface.

12. The stepwise capacitor according to claim 10, wherein the second lower surface is misaligned with regard to the second upper surface.

13. The stepwise capacitor according to claim 10, wherein the height of the second lower surface is lower than the height of the second upper surface.

14. The stepwise capacitor according to claim 10 wherein the inverse stepwise structure further comprising:

a third inverse step having a third lower surface, the third inverse step is disposed on the lower surface of the first step and adjacent to the second inverse step;

wherein the third lower surface is lower than the second lower surface.

15. The stepwise capacitor according to claim 14, wherein the third inverse step is disposed under the second lower surface of the second inverse step.

16. The stepwise capacitor according to claim 14, wherein the third inverse step is disposed next to the second inverse step.

17. The stepwise capacitor according to claim 14, wherein the second inverse step and the third inverse step are disposed with thickness complementary to each other respectively.

18. The stepwise capacitor according to claim 1, wherein the dielectric layer comprising:

a first dielectric layer having a first dielectric coefficient; and

a second dielectric layer having a second dielectric coefficient.

30. A substrate comprising a stepwise capacitor according to claim 1.

31. The substrate according to claim 30, wherein the lower conductive layer having the stepwise structure.

32. The substrate according to claim 31, wherein the stepwise capacitor comprising:

a first step having a first upper surface; and

a second step having a second upper surface;

wherein the second upper surface being higher than the first upper surface.

33. The substrate according to claim 32, wherein the second step is disposed on the first step.

34. The substrate according to claim 33, wherein more than one of the second step being disposed next to each other at a distance on the first step.

35. The substrate according to claim 33, wherein the stepwise structure further comprising:

a third step having a third upper surface, being disposed on the first upper surface and adjacent to the second step;

wherein the third upper surface is higher than the second upper surface.

36. The substrate according to claim 35, wherein the third step is disposed next to the second step.

37. The substrate according to claim 33, wherein the stepwise structure further comprising:

a third step disposed on the upper surface of the second step.

38. The substrate according to claim 32, wherein the upper conductive layer having a cross section in a shape of inverse stepwise structure.

39. The substrate according to claim 38, wherein the inverse stepwise structure comprising:

a first inverse step having a first lower surface; and

a second inverse step having a second lower surface wherein the second lower surface being lower than the first lower surface.

40. The substrate according to claim 39, wherein the second lower surface is aligned to the second upper surface.

41. The substrate according to claim 39, wherein the second lower surface is misaligned with regard to the second upper surface.

42. The substrate according to claim 39, wherein the height of the second lower surface is lower than the height of the second upper surface.

43. The substrate according to claim 39, wherein the inverse stepwise structure further comprising:

a third inverse step having a third lower surface, the third inverse step is disposed on the lower surface of the first step and adjacent to the second inverse step;

wherein the third lower surface is lower than the second lower surface.

44. The substrate according to claim 43, wherein the third inverse step disposed under the second lower surface of the second inverse step.

45. The substrate according to claim 39, wherein the third inverse step is disposed next to the second inverse step.

46. The substrate according to claim 42, wherein the second inverse step and the third inverse step are disposed with a thickness complementary to each other respectively.

47. The substrate according to claim 30, wherein the dielectric layer comprising:

a first dielectric layer having a first dielectric coefficient; and

a second dielectric layer having a second dielectric coefficient

48. The substrate according to claim 30, further comprising:

at least a conductive via, connecting to one of the upper conductive layer and the lower conductive layer.

49. The substrate according to claim 30, wherein the upper conductive layer or the lower conductive layer is embedded in the substrate.

50. The substrate according to claim 30, wherein the upper conductive layer or the lower conductive layer is embedded in the substrate in a form of an entire layer.

51. The substrate according to claim 30, wherein the substrate is a silicon substrate, a chip carrier, a ceramic substrate, a glass substrate, a flexible substrate, or a printed circuit board.

52. The substrate according to claim 30, is made a portion of an integrated circuit package.

53. The substrate according to claim 30 is embedded in another substrate and the stepwise capacitor of the substrate is electrically coupled to a stepwise capacitor of the another substrate.

19. A fabrication method of a stepwise capacitor, comprising:

forming a lower conductive layer having a stepwise structure; and

providing an upper conductive layer and a dielectric layer; and

combining the lower conductive layer, the dielectric layer, and the upper conductive layer to form the stepwise capacitor.

20. The fabrication method according to claim 19, wherein the lower conductive layer is formed by:

providing a first conductive layer;

patterning a first resistive layer on the first conductive layer; and

forming a second conductive layer on the first conductive layer.

21. The fabrication method according to claim 20, further comprising:

patterning a second resistive layer on the second conductive layer;

forming a third conductive layer on the second conductive layer; and

removing the first barrier layer so that the first conductive layer and the patterned second conductive layer are combined to form the lower conductive layer.

22. The fabrication method according to claim 20, wherein the resistive layer is formed on the conductive layer by press bounding or immersion.

23. The fabrication method according to claim 19, wherein the stepwise conductive layer is formed by printing.

24. The fabrication method according to claim 19, wherein the stepwise conductive layer is formed by coating.

25. The fabrication method according to claim 19, wherein the stepwise conductive layer is formed by injecting.

26. The fabrication method according to claim 19, wherein the stepwise conductive layer is formed by sputtering.

27. The fabrication method according to claim 19, wherein the stepwise conductive layer is formed by calendering.

28. The fabrication method according to claim 19, wherein the stepwise conductive layer is formed by molding.

29. The fabrication method according to claim 19, wherein the dielectric layer comprising:

a first dielectric layer having a first dielectric coefficient; and

a second dielectric layer having a second dielectric coefficient.