METHOD FOR MANUFACTURING A CMOS DEVICE HAVING DUAL METAL GATE

• US 20090181504A1
• Filed: 01/14/2008
• Published: 07/16/2009
• Est. Priority Date: 01/14/2008
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Ma, Guang-Hwa, Cheng, Li-Wei, Hsu, Che-Hua, Lin, Chien-Ting, Yang, Chin-Sheng
• Granted Patent: US 8,685,811 B2
• Time in Patent Office: Days
• US Class Current: 438/199
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A method for manufacturing a CMOS device includes providing a substrate having a first active region and a second active region defined thereon, forming a first conductive type transistor and a second conductive type transistor respectively in the first and the second active regions, performing a salicide process, forming an ILD layer, performing a first etching process to remove a first gate of the first conductive type transistor and to form an opening while a high-K gate dielectric layer is exposed in a bottom of the opening, and forming at least a first metal layer in the opening.

Claims

1. A method for manufacturing a complementary metal oxide semiconductor (CMOS) device having dual metal gate comprising steps of:

providing a substrate having a first active region and a second active region defined thereon;

forming a first conductive type transistor and a second conductive type transistor respectively in the first active region and the second active region;

performing a salicide process;

forming an inter-level dielectric (ILD) layer exposing tops of the first conductive type transistor and the second conductive type transistor on the substrate;

performing a first etching process to remove a portion of a first gate of the first conductive type transistor to form an opening in the first active region, and a high-K gate dielectric layer of the first conductive type transistor being exposed in a bottom of the opening; and

forming at least a first metal layer in the opening.

2. The method of claim 1, wherein the step of forming the first conductive type transistor and the second conductive type transistor further comprises:

forming the high-K gate dielectric layer, a TaC layer, and a polysilicon layer on the substrate sequentially;

performing a photolithographic and etching process to etch the polysilicon layer, the TaC layer, and the high-K gate dielectric layer to form the first gate and a second gate respectively in the first active region and the second active region;

forming a first light doped drain (LDD) and a second LDD in the substrate at two sides of the first gate and the second gate, respectively;

forming a spacer on sidewalls of the first gate and the second gate, respectively; and

forming a first source/drain and a second source/drain in the substrate at two sides of the first gate and the second gate, respectively.

3. The method of claim 2 further comprising a step of performing a second etching process after the first etching process, the first etching process is used to remove the polysilicon layer of the first conductive type transistor and the second etching process is used to remove the TaC layer of the first conductive type transistor.

4. The method of claim 2 further comprising a step of forming a protective layer covering the high-K gate dielectric layer in the first active region.

5. The method of claim 4 further comprising a step of performing a third etching process after the first etching process to remove the protective layer and expose the high-K gate dielectric layer.

6. The method of claim 2 further comprising a step of performing a polysilicon oxidation process after forming the first LDD and the second LDD to oxidize the entire or a portion of the polysilicon layer.

7. The method of claim 2 further comprising a step of forming a cap layer on the first gate.

8. The method of claim 7 further comprising a step of performing a fourth etching process before the first etching process to remove the cap layer.

9. The method of claim 2 further comprising a step of forming a contact etch stop layer (CESL) on the substrate before forming the ILD.

10. The method of claim 9 further comprising a step of performing a fifth etching process before the first etching process to remove the CESL on the first gate.

11. The method claim 1, wherein the metal layer comprises MoAlN, W, MoN, TaCNO, TiN, or WN.

12. The method of claim 1 further comprising a step of forming a second metal layer in the opening after forming the first metal layer, and the second metal layer comprises Al, Ti, Ta, W, Nb, Mo, TiN, TiC, TaN, Ti/W, or Ti/TiN.

13. A method for manufacturing a complementary metal oxide semiconductor (CMOS) device having dual metal gate comprising steps of:

providing a substrate having a first active region and a second active region defined thereon;

forming a first conductive type transistor and a second conductive type transistor respectively in the first active region and the second active region;

performing a salicide process;

forming an inter-level dielectric (ILD) layer exposing tops of the first conductive type transistor and the second conductive type transistor on the substrate;

performing a first etching process to remove a portion of a first gate of the first conductive type transistor to form a first opening in the first active region, and a high-K gate dielectric layer of the first conductive type transistor being exposed in a bottom of the first opening;

forming at least a first metal layer in the first opening;

performing a second etching process to remove a portion of a second gate of the second conductive type transistor to form a second opening in the second active region, and a high-K gate dielectric layer of the second conductive type transistor be exposed in a bottom of the second opening; and

forming at least a second metal layer in the second opening.

14. The method of claim 13, wherein the step of forming the first conductive type transistor and the second conductive type transistor further comprises:

forming the high-K gate dielectric layer and a polysilicon layer on the substrate sequentially;

performing a photolithographic and etching process to etch the polysilicon layer and the high-K gate dielectric layer to form the first gate and the second gate respectively in the first active region and the second active region;

forming a first light doped drain (LDD) and a second LDD in the substrate at two sides of the first gate and the second gate, respectively;

forming a spacer on sidewalls of the first gate and the second gate, respectively; and

forming a first source/drain and a second source/drain in the substrate at two sides of the first gate and the second gate, respectively.

15. The method of claim 14 further comprising a step of forming a protective layer covering the high-K gate dielectric layer on the substrate after forming the high-K gate dielectric layer.

16. The method of claim 15 further comprising a step of performing a third etching process after the first etching process to remove the protective layer and expose the high-K gate dielectric layer.

17. The method of claim 13, wherein the first metal layer comprises MoAlN, W, MoN, TaCNO, TiN, or WN.

18. The method of claim 13, wherein the second metal layer comprises TaC or TiAlN.

19. The method of claim 13 further comprising steps of forming a third metal layer respectively in the first opening and the second opening.

20. The method of claim 19, wherein the third metal layer comprises Al, Ti, Ta, W, Nb, Mo, TiN, TiC, TaN, Ti/W, or Ti/TiN.