Method and Structure for Dividing a Substrate into Individual Devices

• US 20090181520A1
• Filed: 07/17/2008
• Published: 07/16/2009
• Est. Priority Date: 10/01/2007
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Kim, Suku, Murphy, James J., Yilmaz, Hamza, Wang, Qi, Reynolds, Matthew, Sim, Gordon, Li, Minhua
• Granted Patent: US 7,951,688 B2
• Time in Patent Office: Days
• US Class Current: 438/462
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for obtaining individual dies from a semiconductor structure is disclosed. The semiconductor structure includes a device layer, and the device layer in turn includes active regions separated by predefined spacings. Thick metal is selectively formed on backside of the device layer such that thick metal is formed on backside of active regions but not on backside of the predefined spacings. The semiconductor structure is then cut along the predefined spacings to separate the active regions with thick metal on their backside into individual dies.

Claims

1. A method for obtaining individual dies from a semiconductor structure that includes a device layer, the device layer in turn including active regions separated by predefined spacings, the method comprising:

selectively forming thick metal on backside of the device layer such that thick metal is formed on backside of active regions but not on backside of the predefined spacings; and

cutting the semiconductor structure along the predefined spacings to separate the active regions with thick metal on their backside into individual dies.

2. The method of claim 1 wherein cutting along the predefined spacings comprises using a die sawing process to cut through the predefined spacings where thick metal is not formed.

3. The method of claim 2 wherein the predefined spacings comprise scribed line regions.

4. The method of claim 1 wherein the thick metal is formed using selective electroplating.

5. The method of claim 1 further comprising:

prior to forming the thick metal layer, forming a seed layer over and in contact with the backside of each active region, each seed layer being separated by an adjacent seed layer by a vertically extending structure; and

inducing a plating current through each seed layer to thereby induce formation of a thick metal from the corresponding seed layer.

6. The method of claim 5 wherein the seed layer includes a metal layer and a diffusion barrier layer.

7. The method of claim 5 wherein the vertically extending structure is formed using a backside alignment masking process which aligns the vertically extending structure with the scribe line regions.

8. The method of claim 1 wherein the device layer includes a FET structure, the FET structure including:

source regions in an upper portion of the device layer,

a topside metal layer contacting the source regions; and

a drain region extending into a lower portion of the device layer, wherein the thick metal is in direct contact with the drain region along the backside of the device layer, the thick metal being thicker than the topside metal layer.

9. A method for obtaining individual dies from a semiconductor structure that includes a device layer, the device layer in turn including active regions separated by predefined spacings, the method comprising:

forming a vertically extending structure along a backside of the predefined spacings such that the vertically extending structure surrounds each active region to thereby form an opening on the backside of each active region;

forming a thick metal in each opening;

cutting through the vertically extending structure to separate the active regions with thick metal on their backside into individual dies.

10. The method of claim 9 wherein the thick metal is formed using selective electroplating.

11. The method of claim 9 further comprising:

prior to forming the thick metal layer, forming a seed layer over and in contact with the backside of each active region and over and in contact with a top surface of the vertically extending structure, the seed layer being discontinuous along sidewalls of the openings.

12. The method of claim 11 wherein forming a thick metal comprises:

inducing a plating current through seed layer portions extending over and in contact with the backside of each active region.

13. The method of claim 11 wherein the seed layer includes a metal layer and a diffusion barrier layer.

14. The method of claim 9 wherein the device layer includes a FET structure, the FET structure including:

source regions in upper portion of the device layer,

a topside metal layer contacting the source regions; and

a drain region extending into a lower portion of the device layer, wherein the thick metal is in direct contact with the drain region along the backside of the device layer, the thick metal being thicker than the topside metal layer.

15. The method of claim 9 wherein the predefined spacings comprise scribed line regions.

16. The method of claim 9 wherein the vertically extending structure is formed using a backside alignment masking process which aligns the vertically extending structure with the scribe line regions.

17. A method for obtaining individual dies from a semiconductor structure that includes a device layer which in turn includes active regions separated by predefined spacings, the method comprising:

forming a thick metal layer on backside of the device layer;

using a masking layer, removing portions of the thick metal layer so that surface regions along a backside of the device layer are exposed such that the exposed surface regions are substantially aligned the predefined spacings, wherein after removing portions of the thick metal layer, islands of thick metal layer remain on the backside of the device layer; and

after removing portions of the thick metal layer, cutting the semiconductor structure along the exposed backside surface regions.

18. The method of claim 17 wherein the predefined spacings comprise scribed line regions.

19. The method of claim 17 wherein the thick metal is formed using blanket electroplating.

20. The method of claim 17 further comprising:

prior to forming the thick metal layer, forming a seed layer over and in contact with backside of the device layer; and

inducing a plating current through the seed layer to thereby induce formation of a thick metal from the seed layer.

21. The method of claim 20 wherein the seed layer includes a metal layer and a diffusion barrier layer.

22. The method of claim 17 wherein the removing step is carried out using a backside alignment masking process to ensure that in cutting the semiconductor structure, the thick metal layer is not cut through.

23. The method of claim 17 wherein the device layer includes a FET structure, the FET structure including:

source regions in an upper portion of the device layer,

a topside metal layer contacting the source regions; and

a drain region extending into a lower portion of the device layer, wherein the thick metal is in direct contact with the drain region along the backside of the device layer, the thick metal being thicker than the topside metal layer.