SEMICONDUCTOR MEMORY DEVICE AND WEAR LEVELING METHOD

• US 20090182936A1
• Filed: 01/09/2009
• Published: 07/16/2009
• Est. Priority Date: 01/11/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: LEE, Tae-Min
• Granted Patent: US 8,209,468 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7211 Wear leveling

Abstract

Disclosed is a semiconductor memory device and wear leveling method thereof. The semiconductor memory device including: a nonvolatile memory having pluralities of memory blocks, at least one of the memory blocks storing erasing counts of the memory blocks; and a memory controller managing wear leveling of the nonvolatile memory. The memory controller adjusts a period of managing the wear leveling with reference to the erasing counts.

Claims

1. A semiconductor memory device comprising:

a nonvolatile memory having a plurality of memory blocks, wherein the nonvolatile memory stores an erase count associated with at least one of the plurality of memory blocks; and

a memory controller executing a wear leveling method in relation to the plurality of memory blocks, wherein the rate of execution for the wear leveling method varies in relation to the erase count.

2. The semiconductor memory device of claim 1, wherein the memory controller increases the rate of execution for the wear leveling method as the erase count increases.

3. The semiconductor memory device of claim 1, wherein the erase count is derived in relation to more than one of the plurality of memory blocks.

4. The semiconductor memory device of claim 3, wherein the memory controller causes a data swap between a highest memory block having a highest current erase count and a lowest memory block having a lowest current erase count.

5. The semiconductor memory device of claim 1, wherein the memory controller determines a reference count in relation to the erase count.

6. The semiconductor memory device of claim 5, wherein the memory controller reduces the reference count as the erase count increases.

7. The semiconductor memory device of claim 5, wherein the memory controller executes the wear leveling method in response to a number of merge operations executed in the nonvolatile memory.

8. The semiconductor memory device of claim 7, wherein the reference count varies in relation to the number of merge operations executed in the nonvolatile memory.

9. The semiconductor memory device of claim 1, wherein the nonvolatile memory comprises:

a memory cell array including the plurality of memory blocks;

a data input/output circuit connected to the memory cell array through a plurality of bit lines to sense data stored in the memory cell array;

a row decoder connected to the memory cell array through a plurality of word lines to select one of the plurality of memory blocks in response to an address; and

a control logic circuit controlling the data input/output circuit and the row decoder in response to a command provided from the memory controller.

10. The semiconductor memory device of claim 9, wherein the control logic circuit zeros the erase count in response to a command provided from the memory controller.

11. A wear leveling method adapted for use in a semiconductor memory device having plurality of memory blocks, the method comprising:

detecting an erase count associated with at least one of the plurality of memory blocks;

determining a reference count in relation to the erase count;

comparing a merge operation count with the reference count; and

executing a wear leveling method in relation to the semiconductor memory in accordance with a result of the comparison.

12. The method of claim 11, wherein a rate of execution for the wear leveling method is increased with an increase in the erase count.

13. The method of claim 12, further comprising:

increasing the merge operation count upon execution of a merge operation between two or more of the plurality of memory blocks.

14. The method of claim 13, wherein the wear leveling method is executed once the merge operation count reaches the reference count, and the reference count is reduced in accordance with an increase of the erase count.

15. The method of claim 11, wherein determining the reference count comprises:

detecting whether the erase count has reached a reference value; and

thereafter,

determining the reference count in accordance with a result of the detection.