Memory Subsystem Hibernation

• US 20090182962A1
• Filed: 08/18/2008
• Published: 07/16/2009
• Est. Priority Date: 01/16/2008
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Khmelnitsky, Vadim, Wakrat, Nir Jacob
• Granted Patent: US 8,892,831 B2
• Time in Patent Office: Days
• US Class Current: 711/162
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In a managed memory subsystem, information associated with the memory subsystem is copied from volatile memory in the memory subsystem to host system memory. The copying can be over a standard interface. Responsive to memory subsystem power up from a powered down state or power loss, the information is copied from the host system memory back to the volatile memory in the memory subsystem, where the information can be used by the memory subsystem to perform memory operations. Transferring information from host system memory to volatile memory in a memory subsystem is faster and more power efficient than transferring the same information from non-volatile memory to volatile memory in the memory subsystem.

Claims

1. A method comprising:

copying information from volatile memory of a managed memory system to memory of a host system coupled to the managed memory system;

responsive to a power-related trigger event,

reading the information from the host system memory; and

storing the information in the volatile memory of the managed memory system.

2. The method of claim 1, wherein the information is related to a state of the managed memory system.

3. The method of claim 1, wherein the managed memory system is a managed NAND memory system.

4. The method of claim 1, wherein the information is copied over a bus that conforms to at least one of the following standard bus protocols:

Advanced Technology Attachment (ATA), MultiMediaCard (MMC) and Secure Digital (SD).

5. The method of claim 1, wherein the volatile memory is accessible by an embedded controller in the managed memory system.

6. The method of claim 2, where the information includes a physical address of non-volatile memory of the managed memory system that is storing the state information.

7. A managed memory system, comprising:

a memory subsystem having volatile memory and non-volatile, the volatile memory and non-volatile memory each storing information related to the memory subsystem; and

a host system coupled to the memory subsystem and including a processor which is operable for copying the information from the non-volatile memory to memory in the host system, and for copying the information back to the non-volatile memory in response to a power related trigger event.

8. The system of claim 7, wherein the information is related to a state of the managed memory system.

9. The system of claim 7, wherein the managed memory system is a managed NAND memory system.

10. The system of claim 7, wherein the information is copied over a bus that conforms to at least one of the following bus protocols:

Advanced Technology Attachment (ATA), MultiMediaCard (MMC) and Secure Digital (SD).

11. The system of claim 7, wherein the volatile memory is accessible by an embedded controller in the managed memory system.

12. The system of claim 8, where the information includes a physical address of non-volatile memory of the managed memory system that is storing the state information.