Large-Page Optimization in Virtual Memory Paging Systems
First Claim
1. A memory management unit of a computer system that employs page tables to map virtual memory pages to physical memory pages, comprising:
- a translation lookaside buffer (TLB) for storing a number of mappings of virtual memory pages to physical memory pages; and
a hardware page walker for accessing the page tables when a mapping of a particular virtual memory page to a particular physical memory page is not stored in the TLB, and causing an incrementing of multi-bit counters that are associated with entries of the page tables.
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Accused Products
Abstract
A computer system that is programmed with virtual memory accesses to physical memory employs multi-bit counters associated with its page table entries. When a page walker visits a page table entry, the multi-bit counter associated with that page table entry is incremented by one. The computer operating system uses the counts in the multi-bit counters of different page table entries to determine where large pages can be deployed effectively. In a virtualized computer system having a nested paging system, multi-bit counters associated with both its primary page table entries and its nested page table entries are used. These multi-bit counters are incremented during nested page walks. Subsequently, the guest operating systems and the virtual machine monitors use the counts in the appropriate multi-bit counters to determine where large pages can be deployed effectively.
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Citations
40 Claims
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1. A memory management unit of a computer system that employs page tables to map virtual memory pages to physical memory pages, comprising:
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a translation lookaside buffer (TLB) for storing a number of mappings of virtual memory pages to physical memory pages; and a hardware page walker for accessing the page tables when a mapping of a particular virtual memory page to a particular physical memory page is not stored in the TLB, and causing an incrementing of multi-bit counters that are associated with entries of the page tables. - View Dependent Claims (2, 3, 4, 5)
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6. In a virtual memory system having page tables, a method for mapping a virtual memory address to a physical memory address, comprising:
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accessing a page table entry of a page table using a first pointer to a physical memory location and a first portion of the virtual memory address; incrementing a multi-bit counter associated with said page table entry; and accessing a physical memory address associated with the virtual memory address using a second pointer to a physical memory location and a second portion of the virtual memory address, wherein the second pointer to the physical memory location is stored in said page table entry. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. In a virtual memory system of a virtual machine having nested page tables and primary page tables, wherein the nested page tables have multiple page table entries, each of which includes a pointer to a host physical memory location, and the primary page tables have multiple page table entries, each of which includes a pointer to a virtualized physical memory location, a method for mapping a virtual memory address to a host physical memory address, comprising:
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retrieving a virtualized physical memory address from a page table entry of one of the primary page tables using a portion of the virtual memory address; accessing a page table entry of a nested page table using a first pointer to a host physical memory location and a first portion of the virtualized physical memory address; incrementing a multi-bit counter associated with the page table entry of said nested page table; and accessing a host physical memory address associated with the virtualized physical memory address using a second pointer to a host physical memory location and a second portion of the virtualized physical memory address, wherein the second pointer to the host physical memory location is stored in the page table entry of said nested page table. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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- 28. A computer system programmed with an operating system that employs virtual memory and page tables to map virtual memory addresses to physical memory addresses, the computer system comprising a first memory unit including the physical memory, and a second memory unit that provides faster memory access than the first memory unit and storing entries for mapping virtual memory pages of various sizes to physical memory pages, wherein when a page table entry in one of the page tables is accessed, a multi-bit counter associated with said page table entry is incremented by one.
- 34. A computer system having hardware resources including a host processor and a host memory, the computer system being programmed with a virtual machine having a virtualized processor and a virtualized physical memory that are operatively coupled to the hardware resources under the control of a virtualization software, wherein the virtual machine is programmed with an operating system that employs virtual memory and primary page tables to map virtual memory addresses to locations in the virtualized physical memory, and when a page table entry in one of the primary page tables is accessed, a multi-bit counter associated with said page table entry is incremented by one.
Specification