PROCESSOR INCLUDING EFFICIENT SIGNATURE GENERATION FOR LOGIC ERROR PROTECTION

• US 20090182991A1
• Filed: 01/10/2008
• Published: 07/16/2009
• Est. Priority Date: 01/10/2008
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Quach, Nhon
• Granted Patent: US 7,865,770 B2
• Time in Patent Office: Days
• US Class Current: 712/222
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3891 organised in groups of units sharing resources, e.g. clusters

Abstract

A processor core includes an instruction decode unit that may dispatch a same integer instruction stream to a plurality of integer execution units operating in lock-step. The processor core also includes signature generation logic that may generate, concurrently with execution of the integer instructions, a respective signature from result signals conveyed on respective result buses in one or more pipeline stages within each of the integer execution units in response to the result signals becoming available. The processor core also includes compare logic that may detect a mismatch between signatures from each of the integer execution units. Further, in response to the compare logic detecting any mismatch, the compare logic may cause instructions causing the mismatch to be re-executed.

Claims

1. A processor core configured to operate in a reliable execution mode, the processor core comprising:

an instruction decode unit configured to dispatch a same integer instruction stream to a plurality of integer execution units;

wherein the plurality of integer execution units is configured to operate in lock-step such that during each clock cycle, the plurality of integer execution units executes a same integer instruction;

signature generation logic coupled to each of the plurality of integer execution units, wherein the signature generation logic is configured to generate a respective signature from result signals conveyed on respective result buses in one or more pipeline stages within each respective one of the plurality of integer execution units in response to the result signals becoming available, wherein the signature generation unit is configured to generate the signatures concurrently with execution of the integer instructions; and

compare logic coupled to the signature generation logic and configured to detect a mismatch between signatures from each of the plurality of integer execution units;

wherein in response to the compare logic detecting any mismatch, the compare logic is configured to cause instructions causing the mismatch to be re-executed.

2. The processor core as recited in claim 1, wherein the compare logic is further configured to compare and detect a mismatch between signatures from each of the plurality of integer execution units prior to results from execution of the same integer instruction stream being placed in a retirement queue.

3. The processor core as recited in claim 1, wherein the decode unit is further configured to consecutively dispatch a same floating-point instruction thread to a floating point unit that is configured to execute the same floating-point instruction thread twice.

4. The processor core as recited in claim 3, wherein the signature generation logic is also coupled to the floating-point unit and configured to generate a signature from result signals conveyed on result buses within the floating point unit, wherein the signature generation unit is configured to generate the signature concurrently with execution of the floating-point instructions.

5. The processor core as recited in claim 4, wherein the compare logic is further configured to detect a mismatch between signatures of results of each execution of instructions in the same floating-point instruction thread.

6. The processor core as recited in claim 5, wherein the compare logic is further configured to compare and detect a mismatch between signatures of results of each execution of instructions in the same floating-point instruction thread prior to the floating-point unit transferring the execution results of the floating-point instruction thread to a retirement queue.

7. The processor core as recited in claim 1, wherein the compare logic is further configured to check results of branch mis-predictions within each of the plurality of integer execution units.

8. The processor core as recited in claim 1, wherein the compare logic is further configured to check for substantially simultaneous accesses to a level two cache by each of the plurality of integer execution units.

9. The processor core as recited in claim 1, wherein the signature generation logic is further configured to generate the respective signature from datapath input signals conveyed on respective datapath input buses in the one or more pipeline stages within each respective one of the plurality of integer execution units.

10. The processor core as recited in claim 1, wherein the signature generation logic is further configured to generate the respective signature using signals corresponding to processor state information within each respective one of the plurality of integer execution units.

11. A method for protecting against logic errors in a processor core, the method comprising:

operating the processor core in a reliable execution mode;

dispatching a same integer instruction stream to a plurality of integer execution units;

operating the plurality of integer execution units in lock-step such that during each clock cycle, the plurality of integer execution units executes a same integer instruction;

signature generation logic generating a respective signature from result signals conveyed on respective result buses in one or more pipeline stages within each respective one of the plurality of integer execution units in response to the result signals becoming available by generating the signatures concurrently with execution of the integer instructions; and

compare logic detecting a mismatch between signatures from each of the plurality of integer execution units;

wherein in response to the compare logic detecting any mismatch, the compare logic causing instructions that caused the mismatch to be re-executed.

12. The method as recited in claim 11, further comprising the compare logic comparing and detecting a mismatch between signatures from each of the plurality of integer execution units prior to results from execution of the same integer instruction stream being placed in a retirement queue.

13. The method as recited in claim 11, further comprising the decode unit consecutively dispatching a same floating-point instruction thread to a floating point unit for execution by the floating-point unit twice.

14. The method as recited in claim 13, further comprising the signature generation logic generating a signature from result signals conveyed on result buses within the floating point unit, by generating the signature concurrently with execution of the floating-point instructions.

15. The method as recited in claim 14, further comprising the compare logic detecting a mismatch between signatures of results of each execution of instructions in the same floating-point instruction thread.

16. The method as recited in claim 15, further comprising the compare logic comparing and detecting a mismatch between signatures of results of each execution of instructions in the same floating-point instruction thread prior to the floating-point unit transferring the execution results of the floating-point instruction thread to a retirement queue.

17. The method as recited in claim 11, further comprising the compare logic checking results of branch mis-predictions within each of the plurality of integer execution units and providing an indication in response to detecting a branch misprediction on one integer execution unit and not another integer execution unit.

18. The method as recited in claim 11, further comprising the compare logic checking for substantially simultaneous accesses to a level two cache by each of the plurality of integer execution units and providing an indication in response to non-substantially simultaneous accesses.

19. The method as recited in claim 11, further comprising generating the respective signature from datapath input signals conveyed on respective datapath input buses in the one or more pipeline stages within each respective one of the plurality of integer execution units.

20. The method as recited in claim 11, further comprising generating the respective signature using signals corresponding to processor state information within each respective one of the plurality of integer execution units.

21. A processor comprising:

a plurality of processor cores, each processor core comprising;

an instruction decode unit configured to dispatch a same integer instruction stream to a plurality of integer execution units;

wherein the plurality of integer execution units is configured to operate in lock-step such that during each clock cycle, the plurality of integer execution units executes a same integer instruction;

signature generation logic coupled to each of the plurality of integer execution units, wherein the signature generation logic is configured to generate a respective signature from result signals conveyed on respective result buses in one or more pipeline stages within each respective one of the plurality of integer execution units in response to the result signals becoming available, wherein the signature generation unit is configured to generate the signatures concurrently with execution of the integer instructions; and

compare logic coupled to the signature generation logic and configured to detect a mismatch between signatures from each of the plurality of integer execution units;

wherein in response to the compare logic detecting any mismatch, the compare logic is configured to cause instructions causing the mismatch to be re-executed.

22. The processor as recited in claim 21, wherein the compare logic is further configured to compare and detect a mismatch between signatures from each of the plurality of integer execution units prior to results from execution of the same integer instruction stream being placed in a retirement queue.