Concurrent processing element system, and method

• US 20090182993A1
• Filed: 12/12/2008
• Published: 07/16/2009
• Est. Priority Date: 12/13/2007
• Status: Active Grant

• Current Assignee: Wave Semiconductor, Inc.
• Original Assignee: Wave Semiconductor, Inc.
• Inventors: Fant, Karl
• Granted Patent: US 8,078,839 B2
• Time in Patent Office: Days
• US Class Current: 712/225
• CPC Class Codes: G06F 15/825 Dataflow computers
• CPC Class Codes: G06F 9/322 for non-sequential address

Abstract

An electronic processing element is disclosed for use in a system having a plurality of processing elements. The electronic processing element includes an input instruction memory, an operation unit, and an output instruction memory. The input instruction memory is configured to store and retrieve a plurality of operation codes and, for each operation code, an associated output instruction memory address. The operation unit is configured to generate an output datum defined by at least a selected operation code and an associated input datum. The output instruction memory is configured to receive the output instruction memory address and to retrieve an address for an input instruction memory of a second processing element. Upon selection of an input instruction memory address and presentation of an associated input datum, the processing element generates an output datum in association with a corresponding input instruction memory address of the second processing element.

Claims

1. An electronic processing element for use in a system having a plurality of processing elements, said first processing element comprising:

(a) an input instruction memory configured to store and retrieve a plurality of operation codes and, for each operation code, an associated output instruction memory address;

(b) an operation unit configured to generate an output datum defined by at least a selected operation code and an associated input datum; and

(c) an output instruction memory configured to receive the output instruction memory address and to retrieve an address for an input instruction memory of a second processing element;

whereby, upon selection of an input instruction memory address and presentation of an associated input datum, the processing element generates an output datum in association with a corresponding input instruction memory address of the second processing element.

2. The processing element of claim 1 wherein the operation unit is configured to generate an output datum defined by at least a selected operation code and two corresponding input datums.

3. The processing element of claim 1 further including a fan-in element coupled to the operation unit and configured to pass an input datum selected from one of a plurality of data sources.

4. The processing element of claim 1 further including a fan-in element coupled to the operation unit and configured

(a) to pass a first input datum selected from one of a plurality of data sources, and

(b) to pass a second input datum selected from one of a plurality of data sources, said second input datum associated with said first input datum.

5. The processing element of claim 1 further including an address arbitration funnel coupled to the input instruction memory and configured to selectively pass a one of a plurality of input instruction memory addresses.

6. The processing element of claim 1 wherein the operation unit is further configured to generate a condition code in response to an operation code and at least one input datum.

7. The processing element of claim 6 wherein the output instruction memory is further configured to retrieve an address for an input instruction memory of a second processing element dependent upon (a) an output instruction memory address retrieved from the input instruction memory, and (b) a condition code generated by the operation unit.

8. The processing element of claim 1 wherein an address for an input instruction memory of the second processing element includes (a) an identification of the second processing element, and (b) an identification of a memory address associated with the second processing element.

9. The processing element of claim 1 wherein the output instruction memory is further configured to retrieve an address for an input instruction memory of a third processing element.

10. The processing element of claim 9 further including a fan-out element configured

(a) to output an output datum to a second processing element in association with an address for an input instruction memory of the second processing element, and

(b) to output the output datum to a third processing element in association with an address for an input instruction memory of the third processing element.

11. A method using a plurality of electronic processing elements to perform a process expressed as a set of predetermined instructions, said method comprising:

(a) providing a plurality of processing units, each processing unit including

(i) an operation unit configured to generate an output datum in response to at least one input datum and an operation code, and

(ii) an instruction memory configured to store and retrieve instructions, said instruction memory including (A) an input instruction memory configured to store and retrieve an operation code and a memory address for an output instruction memory, and (B) an output instruction memory configured to store and retrieve at least one memory address for a subsequent instruction of the process;

(b) storing instructions in instruction memories such that

(i) an instruction memory associated with a first processing element stores a first instruction that produces a datum,

(ii) an instruction memory associated with a second processing element stores a second instruction that operates on the datum, and

(iii) the first instruction includes an address for the second instruction; and

(c) performing the process by

(i) associating data with input memory instruction addresses for instructions operating on the data, and

(ii) communicating associated data and input memory instruction addresses together among processing elements.

12. The method of claim 11 wherein the step of providing a plurality of processing elements provides a processing element that includes:

(a) an operation unit configured to generate an output datum in response to at least two input datums, and

(b) an input instruction memory that retrieves an operation code when the processing element receives two datums associated with a single input instruction memory address.

13. The method of claim 11 wherein the step of providing a plurality of processing elements provides a processing element that has an arbitration funnel coupled to an instruction memory and configured to selectively pass one of a plurality of input instruction memory addresses.

14. The method of claim 11 wherein:

(a) the process is expressed with a conditional instruction that, depending on a condition, is followed by one of at least two possible instructions; and

(b) the step of performing the process associates a datum with an instruction memory addresses for one of the at least two possible instructions selected according to the condition.

15. The method of claim 14 wherein the step of providing a plurality of processing elements provides:

(a) an operation unit configured to generate a condition code depending upon the condition; and

(b) an instruction memory including an output instruction memory configured

(i) to store input memory instruction addresses for the at least two possible instructions and

(ii) selectively to retrieve one of the input instruction memory addresses according to the condition code.

16. The method of claim 14 wherein, for the conditional instruction, the step of storing instructions in instruction memories stores (a) an address for a first of the at least two next instructions and (b) an address for a second of the at least two next instructions.

17. The method of claim 11 wherein

(a) the process is expressed with an instruction that generates a datum used by at least two subsequent instructions, and

(b) the step of providing a plurality of processing elements provides an output instruction memory configured to retrieve input instruction memory addresses for the at least two subsequent instructions upon generation of the datum.

18. The method of claim 11 wherein:

(a) the process is expressed with an instruction that generates a datum used by at least two subsequent instructions, and

(b) the step of performing the process associates the datum with input memory instruction addresses for the at least two subsequent instructions.

19. An electronic method using a plurality of processing elements to perform at least two processes concurrently, said first process expressed as a first set of predetermined instructions and said second process expressed as a second set of predetermined instructions, said method comprising:

(a) providing a plurality of processing units, each processing unit including

(i) an operation unit configured to generate an output datum in response to at least one input datum and an operation code, and

(ii) an instruction memory configured to store and retrieve instructions, said instruction memory including (A) an input instruction memory configured to store and retrieve an operation code and a memory address for an output instruction memory, and (B) an output instruction memory configured to store and retrieve at least one memory address for a subsequent instruction of a process;

(b) storing the first set of instructions in instruction memories such that

(i) an instruction memory associated with a first processing element stores a first instruction of the first set of instructions that produces a first datum,

(ii) an instruction memory associated with a second processing element stores a second instruction of the first set of instructions that operates on the first datum, and

(iii) the first instruction of the first set of instructions includes an address for the second instruction of the first set;

(c) storing the second set of instructions in instruction memories such that

(i) an instruction memory associated with a first processing element stores a first instruction of the second set of instructions that produces a second datum,

(ii) an instruction memory associated with a third processing element stores a second instruction of the second set of instructions that operates on the second datum, and

(iii) the first instruction of the second set of instructions includes an address for the second instruction of the second set; and

(d) performing the processes concurrently by, for both process

(i) associating data with input memory instruction addresses for instructions operating on the data, and

(ii) communicating associated data and input memory instruction addresses together among processing elements.

20. The method of claim 19 wherein the third processing element is the second processing element.