PROCESSOR INCLUDING HYBRID REDUNDANCY FOR LOGIC ERROR PROTECTION
First Claim
1. A processor core configured to operate in a reliable execution mode, the processor core comprising:
- an instruction decode unit configured to dispatch a same integer instruction stream to a plurality of integer execution units and to consecutively dispatch a same floating-point instruction thread to a floating point unit;
wherein the plurality of integer execution units is configured to operate in lock-step such that during each clock cycle, the plurality of integer execution units executes a same integer instruction;
wherein the floating-point unit is configured to execute the same floating-point instruction stream twice;
compare logic coupled to the plurality of integer execution units and the floating-point unit, wherein prior to instructions in the same integer instruction stream retiring, the compare logic is configured to detect a mismatch between execution results from each of the plurality of integer execution units;
wherein prior to the floating-point unit transferring the execution results of the floating-point instruction stream out of the floating-point unit, the compare logic is further configured to detect a mismatch between results of execution of each consecutive floating-point instruction stream;
wherein in response to the compare logic detecting any mismatch, the compare logic is configured to cause instructions causing the mismatch to be re-executed.
3 Assignments
0 Petitions
Accused Products
Abstract
A processor core includes an instruction decode unit that may dispatch a same integer instruction stream to a plurality of integer execution units and may consecutively dispatch a same floating-point instruction stream to a floating-point unit. The integer execution units may operate in lock-step such that during each clock cycle, each respective integer execution unit executes the same integer instruction. The floating-point unit may execute the same floating-point instruction stream twice. Prior to the integer instructions retiring, compare logic may detect a mismatch between execution results from each of the integer execution units. In addition, prior to the results of the floating-point instruction stream transferring out of the floating-point unit, the compare logic may also detect a mismatch between results of execution of each consecutive floating-point instruction stream. Further, in response to detecting any mismatch, the compare logic may cause instructions causing the mismatch to be re-executed.
63 Citations
20 Claims
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1. A processor core configured to operate in a reliable execution mode, the processor core comprising:
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an instruction decode unit configured to dispatch a same integer instruction stream to a plurality of integer execution units and to consecutively dispatch a same floating-point instruction thread to a floating point unit; wherein the plurality of integer execution units is configured to operate in lock-step such that during each clock cycle, the plurality of integer execution units executes a same integer instruction; wherein the floating-point unit is configured to execute the same floating-point instruction stream twice; compare logic coupled to the plurality of integer execution units and the floating-point unit, wherein prior to instructions in the same integer instruction stream retiring, the compare logic is configured to detect a mismatch between execution results from each of the plurality of integer execution units; wherein prior to the floating-point unit transferring the execution results of the floating-point instruction stream out of the floating-point unit, the compare logic is further configured to detect a mismatch between results of execution of each consecutive floating-point instruction stream; wherein in response to the compare logic detecting any mismatch, the compare logic is configured to cause instructions causing the mismatch to be re-executed. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for protecting against logic errors in a processor core, the method comprising:
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operating the processor core in a reliable execution mode; dispatching a same integer instruction stream to a plurality of integer execution units and consecutively dispatching a same floating-point instruction stream to a floating point unit; operating the plurality of integer execution units in lock-step such that during each clock cycle, the plurality of integer execution units executes a same integer instruction; the floating-point unit executing the same floating-point instruction stream twice; compare logic performing a comparison and detecting a mismatch between execution results from each of the plurality of integer execution units prior to instructions in the same integer instruction stream retiring; compare logic performing a comparison and detecting a mismatch between results of execution of each consecutive floating-point instruction stream prior to the floating-point unit transferring the execution results of the floating-point instruction stream out of the floating-point unit; re-executing instructions caused the mismatch in response to detecting any mismatch. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A processor comprising:
a plurality of processor cores, each processor core comprising; an instruction decode unit configured to dispatch a same integer instruction stream to a plurality of integer execution units and to consecutively dispatch a same floating-point instruction thread to a floating point unit; wherein the plurality of integer execution units is configured to operate in lock-step such that during each clock cycle, the plurality of integer execution units executes a same integer instruction; wherein the floating-point unit is configured to execute the same floating-point instruction stream twice; compare logic coupled to the plurality of integer execution units and the floating-point unit, wherein prior to instructions in the same integer instruction stream retiring, the compare logic is configured to detect a mismatch between execution results from each of the plurality of integer execution units; wherein prior to the floating-point unit transferring the execution results of the floating-point instruction stream out of the floating-point unit, the compare logic is further configured to detect a mismatch between results of execution of each consecutive floating-point instruction stream; wherein in response to the compare logic detecting any mismatch, the compare logic is configured to cause instructions causing the mismatch to be re-executed. - View Dependent Claims (20)
Specification