DOUBLE DATA RATE TEST INTERFACE AND ARCHITECTURE

• US 20090183040A1
• Filed: 03/25/2009
• Published: 07/16/2009
• Est. Priority Date: 08/03/2006
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Whetsel, Lee D.
• Granted Patent: US 7,770,083 B2
• Time in Patent Office: Days
• US Class Current: 714/727
• CPC Class Codes: G01R 31/3172 Optimisation aspects, e.g. using functional pin as test pin, pin multiplexing
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318555 Control logic

Abstract

A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The reduced device test interface is achieved using a double data rate (DDR) signaling technique between the tester and the device. The DDR test interface allows the tester to interface to test circuits within the device, such as IEEE 1500 and/or IEEE 1149.1 test circuits, to provide high test data bandwidth to the test circuits using a minimum of test interface signals. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. Additional features and embodiments of the device test architecture and reduced test interface are also disclosed.

Claims

1. An integrated circuit comprising;

functional circuitry for providing the functionality of the integrated circuit,

functional leads coupled to the functional circuitry for providing functional input and output signals,

test circuitry for testing the functional circuitry,

a double data rate input circuit having an output bus coupled to the test circuitry and having an input bus for receiving external test data and a clock input for receiving an external clock input, said double data rate input circuit receiving external test data on both the rising and falling edges of the clock input.