ADAPTING SCAN-BIST ARCHITECTURES FOR LOW POWER OPERATION
First Claim
Patent Images
1. A scan BIST test circuit, within an integrated circuit, comprising:
- A. a plurality of scan paths each having a scan input, scan output, and a control input;
B. a generator circuit having a control input and a stimulus data output;
C. a compactor circuit having a control input and a response data input;
D. a control circuit providing control output to said control inputs of said scan path, generator circuit, and compactor circuit;
E. a first connection formed between said stimulus data output of said generator circuit and all of said scan inputs of said plurality of scan paths; and
F. a second connection selectively formed between said response data input of said compactor circuit and ones_of said scan outputs of said plurality of scan paths.
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Abstract
A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known art. The changes between the known art Scan-BIST architecture and the low power Scan-BIST architecture involve modification of the known scan path into scan path 502, to insert scan paths A 506, B 508 and C 510, and the insertion of an adaptor circuit 504 in the control path 114 between controller 110 and scan path 502.
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1 Claim
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1. A scan BIST test circuit, within an integrated circuit, comprising:
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A. a plurality of scan paths each having a scan input, scan output, and a control input; B. a generator circuit having a control input and a stimulus data output; C. a compactor circuit having a control input and a response data input; D. a control circuit providing control output to said control inputs of said scan path, generator circuit, and compactor circuit; E. a first connection formed between said stimulus data output of said generator circuit and all of said scan inputs of said plurality of scan paths; and F. a second connection selectively formed between said response data input of said compactor circuit and ones_of said scan outputs of said plurality of scan paths.
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Specification