Method, System, and Program Product for Automated Verification of Gating Logic Using Formal Verification
5 Assignments
0 Petitions
Accused Products
Abstract
Gating rules for a device design containing microelectronic devices are tested using formal verification. Testbench design code is generated for a device design from a design source containing hardware design language code. A formal verification process on the testbench device code determines whether the devices within the device design will be stable or unstable under a gating condition. If the test shows a design is unstable under the gating condition; it is indicated that a hardware design fix for the device design is required. If not, the test ends.
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Citations
33 Claims
- 1. (canceled)
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3. (canceled)
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8. (canceled)
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9. A system for testing a multi-domain microelectronic circuit having Built In Self Testing (BIST) circuitry employing formal verification comprising:
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said system building a formal verification model comprising a testbench hardware design language code and the hardware design language for a design under test to provide a design verification tool by the steps of; generating testbench hardware design language code from the design source hardware design language code, and building a formal verification model comprising the testbench hardware design language code and the hardware design language for the design under test for provision thereof to a design verification tool. - View Dependent Claims (10)
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11. (canceled)
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17. (canceled)
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19. (canceled)
- 23. (canceled)
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24. A method of testing to verify gating rules for a device design containing microelectronic circuits, latches and/or registers by employing a formal verification process comprising the steps as follows:
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generating testbench design code for a device design from a design source containing hardware design language code; performing a formal verification process on the testbench device code to determine whether the microelectronic circuits, latches, and/or registers within the device design will be stable or unstable under a gating condition; then indicating that a hardware design fix for the device design is required if the formal verification process shows that the device design is unstable under the gating condition;
orthen ending the test with respect to said device design if the formal verification process shows that the device design is stable under the gating condition. - View Dependent Claims (26, 27)
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28. A system for testing a multi-domain microelectronic circuit having Built In Self Testing (BIST) circuitry employing formal verification comprising:
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said system testing to verify gating rules for a device design containing microelectronic circuits, latches, and/or registers by employing a formal verification process comprising the steps as follows; generating testbench design code for a device design from a design source containing hardware design language code; performing a formal verification process on the testbench device code to determine whether the latches and/or registers within the device design will be stable or unstable under a gating condition; then indicating that a hardware design fix for the device design is required if the formal verification process shows that the device design is unstable under the gating condition;
orthen ending the test with respect to said device design if the formal verification process shows that the device design is stable under the gating condition. - View Dependent Claims (12, 13, 14, 15, 16, 29, 30)
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31. A program product comprising a computer useable medium including a computer readable program, wherein the computer readable program when executed on a computer causes the computer employing formal verification to control and configure a system for testing a multi-domain microelectronic circuit having Built In Self Testing (BIST) circuitry,
said system testing to verify gating rules for a device design containing microelectronic circuits, latches and/or registers by employing a formal verification process comprising the steps as follows: -
said system generating testbench design code for a device design from a design source containing hardware design language code; said system performing a formal verification process on the testbench device code to determine whether the microelectronic circuits, latches and/or registers within the device design will be stable or unstable under a gating condition; said system then indicating that a hardware design fix for the device design is required if the formal verification process shows that the device design is unstable under the gating condition;
orsaid system then ending the test with respect to said device design if the formal verification process shows that the device design is stable under the gating condition. - View Dependent Claims (18, 20, 21, 22, 32, 33)
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Specification