Non-volatile memory device and method of fabricating the same

• US 20090184360A1
• Filed: 10/03/2008
• Published: 07/23/2009
• Est. Priority Date: 01/18/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Yoon-dong, Kim, Won-joo, Jin, Young-gu, Kim, Suk-pil, Lee, Seung-hoon
• Granted Patent: US 7,863,672 B2
• Time in Patent Office: Days
• US Class Current: 257/319
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

Provided are a non-volatile memory device that may expand to a stacked structure and may be more easily highly integrated and an economical method of fabricating the non-volatile memory device. The non-volatile memory device may include at least one semiconductor column. At least one first control gate electrode may be arranged on a first side of the at least one semiconductor column. At least one second control gate electrode may be arranged on a second side of the at least one semiconductor column. A first charge storage layer may be between the at least one first control gate electrode and the at least one semiconductor column. A second charge storage layer may be between the at least one second control gate electrode and the at least one semiconductor column.

Claims

1. A non-volatile memory device comprising:

at least one semiconductor column;

at least one first control gate electrode arranged on a first side of the at least one semiconductor column;

at least one second control gate electrode arranged on a second side of the at least one semiconductor column;

a first charge storage layer between the at least one first control gate electrode and the at least one semiconductor column; and

a second charge storage layer between the at least one second control gate electrode and the at least one semiconductor column.

2. The non-volatile memory device of claim 1, wherein the at least one first control gate electrode and the at least second control gate electrode are arranged to face each other with the at least one semiconductor column therebetween.

3. The non-volatile memory device of claim 1, further comprising:

a first tunneling insulating layer between the at least one semiconductor column and the first charge storage layer; and

a first blocking insulating layer between the first charge storage layer and the at least one first control gate electrode.

4. The non-volatile memory device of claim 1, further comprising:

a second tunneling insulating layer between the at least one semiconductor column and the second charge storage layer; and

a second blocking insulating layer between the second charge storage layer and the at least one second control gate electrode.

5. The non-volatile memory device of claim 1, wherein the at least one semiconductor column is vertically extended on a substrate.

6. The non-volatile memory device of claim 5, wherein the at least one first control gate electrode includes a plurality of first control gate electrodes stacked on the at least one semiconductor column, and

the at least one second control gate electrode includes a plurality of second control gate electrodes stacked on the at least one semiconductor column.

7. The non-volatile memory device of claim 6, wherein the first charge storage layer is a charge trapping type and extends across the plurality of first control gate electrodes and on the at least one semiconductor column.

8. The non-volatile memory device of claim 6, wherein the second charge storage layer is a charge trapping type and extends across the plurality of second control gate electrodes and on the at least one semiconductor column.

9. The non-volatile memory device of claim 6, further comprising

interlayer insulating layers between the plurality of first control gate electrodes and between the plurality of second control gate electrodes.

10. The non-volatile memory device of claim 1, wherein the at least one semiconductor column includes a plurality of semiconductor columns between the at least one first control gate electrode and the at least one second control gate electrode.

11. The non-volatile memory device of claim 10, wherein the first charge storage layer extends across a first side of the plurality of semiconductor columns, and the second charge storage layer extends across a second side of the plurality of semiconductor columns.

12. The non-volatile memory device of claim 11, wherein the first charge storage layer and the second charge storage layer are connected to each other and are of a charge trapping type.

13. The non-volatile memory device of claim 1, wherein the at least one semiconductor column includes a plurality of semiconductor columns,

the at least one first control gate electrode includes a plurality of first control gate electrodes stacked along a first side of the plurality of semiconductor columns, and

the at least one second control gate electrode includes a plurality of second control gate electrodes stacked along a second side of the plurality of semiconductor columns.

14. The non-volatile memory device of claim 13, further comprising:

a plurality of first word lines stacked as multiple layers to be connected to the plurality of first control gate electrodes; and

a plurality of second word lines stacked as multiple layers to be connected to the plurality of second control gate electrodes.

15. The non-volatile memory device of claim 14, wherein the plurality of first word lines and the plurality of second word lines are arrranged on opposing sides of the non-volatile memory device, separate from each other, with the plurality of semiconductor columns therebetween.

16. The non-volatile memory device of claim 13, wherein the plurality of semiconductor columns are arranged as a matrix, and the first charge storage layer and the second charge storage layer form a single charge storage layer by being connected to each other and surrounding semiconductor columns arranged in each column of the matrix.

17. A method of fabricating a non-volatile memory device, the method comprising:

providing at least one conductive layer;

forming at least one trench in the at least one conductive layer;

forming a charge storage layer on an inner surface of the at least one trench;

forming at least one semiconductor column in the at least one trench on which the charge storage layer is formed; and

patterning the at least one conductive layer to form at least one first control gate electrode and at least one second control gate electrode separate from one another with the at least one semiconductor column therebetween.

18. The method of claim 17, wherein forming the at least one semiconductor column includes:

forming a semiconductor layer on the charge storage layer to fill the at least one trench; and

patterning the semiconductor layer to form a plurality of semiconductor columns separate from one another in the at least one trench.

19. The method of claim 17, further comprising:

forming a blocking insulating layer on an inner surface of the at least one trench before forming the charge storage layer; and

forming a tunneling insulating layer on the charge storage layer after forming the charge storage layer.

20. The method of claim 17, wherein the at least one conductive layer includes a plurality of conductive layers stacked upon one another.

21. The method of claim 20, wherein the at least one first control gate electrode includes a plurality of first control gate electrodes that are formed of portions of the plurality of conductive layers and are stacked along a first side of the at least one semiconductor column, and

the at least one second control gate electrode includes a plurality of second control gate electrodes that are formed of portions of the plurality of conductive layers and are stacked along a second side of the at least one semiconductor column.

22. The method of claim 20, wherein the at least one trench includes a plurality of trenches in the plurality of conductive layers.

23. The method of claim 22, wherein the at least one semiconductor column includes a plurality of semiconductor columns in the plurality of trenches.

24. The method of claim 22, wherein the at least one first control gate electrode includes a plurality of first control gate electrodes that are formed of portions of the plurality of conductive layers and are stacked along a first side of the plurality of semiconductor columns, and

the at least one second control gate electrode includes a plurality of second control gate electrodes that are formed of portions of the plurality of conductive layers and are stacked along a second side of the plurality of semiconductor columns.

25. The method of claim 24, further comprising:

forming a plurality of first word lines defined as portions of the plurality of conductive layers and stacked as multiple layers to be connected to the plurality of first control gate electrodes; and

forming a plurality of second word lines defined as portions of the plurality of conductive layers and stacked as multiple layers to be connected to the plurality of second control gate electrodes.