ARRAY OF MUTUALLY ISOLATED, GEIGER-MODE, AVALANCHE PHOTODIODES AND MANUFACTURING METHOD THEREOF

• US 20090184384A1
• Filed: 01/20/2009
• Published: 07/23/2009
• Est. Priority Date: 01/18/2008
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Sanfilippo, Delfo Nunziato, Fallica, Piero Giorgio
• Granted Patent: US 8,778,721 B2
• Time in Patent Office: Days
• US Class Current: 257/432
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 27/14629 Reflectors
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 31/107 the potential barrier working in avalanche mode, e.g. avalanche photodiodes

Abstract

An embodiment of array of Geiger-mode avalanche photodiodes, wherein each photodiode is formed by a body of semiconductor material, having a first conductivity type and housing an anode region, of a second conductivity type, facing a top surface of the body, a cathode-contact region, having the first conductivity type and a higher doping level than the body, facing a bottom surface of the body, an insulation region extending through the body and insulating an active area from the rest of the body, the active area housing the anode region and the cathode-contact region. The insulation region is formed by a first mirror region of polycrystalline silicon, a second mirror region of metal material, and a channel-stopper region of dielectric material, surrounding the first and second mirror regions.

Claims

1. An array of Geiger-mode avalanche photodiodes, comprising a body of semiconductor material of a first conductivity type, having a top surface and a bottom surface, wherein each photodiode comprises:

an anode region, of the second conductivity type, extending inside said body and facing said top surface;

a cathode region of the first conductivity type and a higher doping level than said body, extending inside said body; and

an insulation region extending through said body and insulating an active area from the rest of said body, the active area housing the anode region, said insulation region comprising a first mirror region of metal material;

wherein said cathode region comprises a cathode-contact region, facing said bottom surface, and a resistive region defining a vertical quenching resistor extending between said anode region and said cathode-contact region.

2. The array according to claim 1, wherein said insulation region moreover comprises a second mirror region of polycrystalline silicon having said first conductivity type, extending underneath said first mirror region, and a channel-stopper region of dielectric material, surrounding said first and second mirror regions.

3. The array according to claim 1, wherein said resistive region comprises a substrate having the first conductivity type, arranged above said cathode-contact region, and an epitaxial layer having the first conductivity type, extending above said substrate and housing said anode region, said cathode-contact region having a first doping level, said substrate having a second doping level lower than said first doping level, and said epitaxial layer having a third doping level intermediate between said first and second doping levels.

4. The array according to claim 3, wherein said cathode region comprises an enrichment region, having the first conductivity type and a fourth doping level, higher than said second and third doping levels, the enrichment region extending in said epitaxial layer inside said active area, underneath and in direct contact with the first anode region.

5. The array according to claim 1, wherein said cathode region comprises a substrate having the first conductivity type, arranged above said cathode-contact region and housing said anode region, said cathode-contact region having a first doping level, and said substrate having a second doping level lower than said first doping level.

6. The array according to claim 5, wherein said cathode region comprises an enrichment region, having the first conductivity type and a higher doping level than said second doping level, said enrichment region extending in said substrate, inside said active area, underneath and in direct contact with the first anode region.

7. The array according to claim 1, wherein an annular guard region, of the second conductivity type and a lower doping level than said anode region, extends inside said active area, facing the top surface, surrounding and in direct contact with said first anode region.

8. The array according to claim 1, comprising an anti-reflection coating region extending over said top surface.

9. The array according to claim 8, wherein said anti-reflection coating region comprises a bottom coating layer extending over said top surface and a top coating layer extending over said bottom coating layer.

10. The array according to claim 9, wherein said bottom coating layer is an oxide layer and said top coating layer is a nitride layer.

11. The array according to claim 1, wherein a metal cathode region extends underneath and in direct electrical contact with said cathode-contact region.

12. A method for manufacturing an array of Geiger-mode avalanche photodiodes, comprising the steps of:

forming a body of semiconductor material having a first conductivity type, a top surface, and a bottom surface;

forming, inside said body and facing said top surface, an anode region of the second conductivity type;

forming, inside said body, a cathode region having the first conductivity type and a higher doping level than said body; and

forming, inside said body, an insulation region extending through said body and surrounding the anode region, forming an insulation region comprising forming a mirror region of metal material,

wherein the forming said cathode region comprises;

forming a cathode-contact region, facing said bottom surface; and

forming a resistive region defining a vertical quenching resistor, extending between said anode region and said cathode-contact region.

13. The method according to claim 12, wherein the step of forming said insulation region comprises forming a trench extending within the body;

forming a channel-stopper layer of dielectric material inside said trench;

filling a bottom portion of said trench with polycrystalline silicon so as to form a first mirror region; and

filling a top portion of said trench with metal material so as to form said second mirror region.

14. The method according to claim 12, wherein forming a channel-stopper layer comprises growing a thin oxide coating inside said trench and depositing a thick oxide coating layer inside said trench on top of and in direct contact with said thin coating layer.

15. The method according to claim 12, wherein the step of forming said resistive region comprises forming a substrate having the first conductivity type and a lower doping level than said cathode-contact region;

and forming, above said substrate, an epitaxial layer having the first conductivity type and a doping level intermediate between a doping level of said cathode-contact region and a doping level of said substrate.

16. The method according to claim 12, comprising introducing dopant species having the first conductivity type inside said epitaxial layer underneath the anode region so as to form an enrichment region in direct contact with the anode region, said enrichment region having the first conductivity type and a higher doping level than said epitaxial layer.

17. The method according to claim 12, wherein forming said resistive region comprises forming a substrate having the first conductivity type and a doping lower level than the cathode-contact region, above said cathode-contact region.

18. The method according to claim 17, comprising introducing dopant species having the first conductivity type inside said substrate underneath the anode region so as to form an enrichment region, underneath and in direct contact with the anode region, said enrichment region having the first conductivity type and a higher doping level than said substrate.

19. The method according to claim 12, comprising introducing dopant species of the second conductivity type inside said epitaxial layer so as to form a guard region facing said surface, laterally and in direct contact with said anode region, said guard region having a lower doping level than said anode region.

20. The method according to claim 12, comprising the step of forming an anti-reflection coating region on top of said top surface.

21. The method according to claim 20, wherein forming said anti-reflection coating region comprises forming an oxide bottom coating layer on top of said top surface and forming a nitride coating layer on top of said bottom coating layer.

22. The method according to claim 12, wherein forming a body comprises providing a wafer of semiconductor material and, before forming said cathode-contact region, grinding said wafer and reducing the thickness of the wafer to obtain said bottom surface.

23. The method according to claim 12, comprising forming a cathode metal region extending underneath and in direct electrical contact with said bottom surface.

24. An avalanche photo diode, comprising:

a semiconductor material;

an anode disposed in the semiconductor material;

a cathode disposed in the semiconductor material and contiguous with the anode;

a cathode contact disposed over the semiconductor material;

a resistive region disposed in the semiconductor material between and contiguous with the cathode and the cathode contact; and

an insulation region disposed in the semiconductor material around the cathode and the anode.

25. The avalanche photo diode of claim 24 wherein:

the semiconductor material comprises a substrate and an epitaxial layer contiguous with the substrate;

the anode and the cathode are disposed on the epitaxial layer;

the resistive region is disposed in the substrate and in the epitaxial layer;

the cathode contact is disposed over a side of the substrate that is opposite from the epitaxial layer; and

the insulating region is disposed in the substrate and in the epitaxial layer.

26. The avalanche photo diode of claim 24 wherein:

the semiconductor material comprises a substrate and an epitaxial layer contiguous with the substrate;

the anode and the cathode are disposed on the epitaxial layer;

the resistive region is disposed in the substrate and in the epitaxial layer;

the cathode contact is disposed in the substrate; and

the insulating region is disposed in the substrate and in the epitaxial layer.

27. The avalanche photo diode of claim 24 wherein:

the anode is more highly doped than the cathode; and

the cathode is more highly doped than the resistive region.

28. The avalanche photo diode of claim 24 wherein the resistive region has a same conductivity as the cathode.

29. The avalanche photo diode of claim 24 wherein the cathode contact comprises:

a first portion disposed in the semiconductor layer; and

a second metal portion disposed over the first portion.

30. The avalanche photo diode of claim 24, further comprising a guard ring disposed in the semiconductor material around and contiguous with the anode and having a same conductivity as the anode.

31. The avalanche photo diode of claim 24, further comprising a wavelength-selective coating disposed over the anode.

32. The avalanche photo diode of claim 24 wherein the insulation region is disposed in the semiconductor material around the resistive region.

33. The avalanche photo diode of claim 24 wherein the insulation region completely surrounds the cathode and the anode.

34. The avalanche photo diode of claim 24 wherein the insulation region comprises:

a trench disposed in the semiconductor material around the anode and the cathode;

an insulator lining the trench; and

a mirror disposed within the lined trench.

35. An integrated circuit, comprising:

a semiconductor die;

array of avalanche photo diodes disposed in the die, each of the photo diodes comprising,

a respective anode disposed in the die,

a respective cathode disposed in the die and contiguous with the anode,

a respective cathode contact disposed over the die, and

a respective resistive region disposed in the die between and contiguous with the cathode and the cathode contact; and

insulation regions disposed in the die between adjacent ones of the photodiodes.

36. A system, comprising:

a first integrated circuit, comprising

a first semiconductor die,

array of avalanche photo diodes disposed in the die, each of the photo diodes comprising,

a respective anode disposed in the die,

a respective cathode disposed in the die and contiguous with the anode,

a respective cathode contact disposed over the die, and

a respective resistive region disposed in the die between and contiguous with the cathode and the cathode contact, and

insulation regions disposed in the die between adjacent ones of the photodiodes; and

a second integrated circuit coupled to the first integrated circuit.

37. The system of claim 36 wherein the second integrated circuit is disposed on the first die.

38. The system of claim 36 wherein the second integrated circuit is disposed on a second die separate from the first die.

39. The system of claim 36 wherein the second integrated circuit comprises a controller.

40. A method, comprising:

forming an anode in a semiconductor material;

forming in the semiconductor material a cathode contiguous with the anode;

forming a cathode contact over the semiconductor material;

forming in the semiconductor material a resistive region between and contiguous with the cathode and the cathode contact; and

forming in the semiconductor material an insulating region around the anode and the cathode.

41. The method of claim 40 wherein:

forming the anode comprises forming the anode in a epitaxial layer of the semiconductor material;

forming the cathode comprises forming the cathode in the epitaxial layer;

forming the resistive region comprises forming the resistive region in a substrate of the semiconductor material;

forming the cathode contact comprises forming a portion of the cathode contact over the substrate; and

forming the insulating region comprises forming the insulating region in the epitaxial layer and in the substrate.

42. The method of claim 40 wherein:

forming the anode comprises forming the anode in a epitaxial layer of the semiconductor material;

forming the cathode comprises forming the cathode in the epitaxial layer;

forming the resistive region comprises forming the resistive region in a substrate of the semiconductor material;

forming the cathode contact comprises forming a portion of the cathode contact in the substrate; and

forming the insulating region comprises forming the insulating region in the epitaxial layer and in the substrate.

43. The method of claim 40, further comprising:

doping the anode with a first dopant concentration; and

doping the cathode with a second doping concentration that is less than the first concentration.

44. The method of claim 40, further comprising doping the resistive region to have a same conductivity type as the cathode.

45. The method of claim 40, further comprising forming in the semiconductor layer a guard region around and contiguous with the anode and having a same conductivity as the anode.

46. The method of claim 40, further comprising forming an anti-reflective coating over the anode.

47. The method of claim 40 wherein forming the insulating region comprises forming the insulating region around at least a portion of the resistive region.

48. The method of claim 40 wherein forming the insulating region comprises:

forming in the semiconductor material a trench around the anode and the cathode;

lining the trench with an insulator; and

forming a reflective material in the lined trench.