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High performance system-on-chip inductor using post passivation process

  • US 20090184394A1
  • Filed: 02/04/2009
  • Published: 07/23/2009
  • Est. Priority Date: 12/21/1998
  • Status: Abandoned Application
First Claim
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1. A system-on-chip structure comprising:

  • a silicon substrate;

    a metallization structure over said silicon substrate, wherein said metallization structure comprises a first interconnect layer over said silicon substrate and a second interconnect layer over said first interconnect layer;

    a first dielectric layer between said first and second interconnect layers;

    a passivation layer over said metallization structure and over said first dielectric layer, wherein said passivation layer comprises a nitride layer;

    a polymer layer on said passivation layer, wherein said polymer layer has a thickness between 2 and 150 micrometers and greater than that of said passivation layer; and

    a capacitor on said polymer layer, wherein said capacitor comprises a lower plate on said polymer layer, an upper plate over said lower plate and a second dielectric layer between said upper and lower plates, wherein said lower plate has a thickness between 0.5 and 20 micrometers, said upper plate has a thickness between 0.5 and 20 micrometers, and said second dielectric layer has a thickness between 500 and 50,000 angstroms, wherein said lower plate comprises a first metal layer and a first electroplated copper layer on said first metal layer, and wherein said upper plate comprises a second metal layer and a second electroplated copper layer on said second metal layer.

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