INPUT/OUTPUT (I/O) BUFFER

• US 20090184395A1
• Filed: 01/23/2008
• Published: 07/23/2009
• Est. Priority Date: 01/23/2008
• Status: Abandoned Application

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Jao, Che-Yuan
• Application Number:
  US12/018,206
• Publication Number:
  US 20090184395A1
• Time in Patent Office: Days
• US Class Current: 257/536
• CPC Class Codes: H01L 27/0288 using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps

Abstract

An I/O buffer including an I/O circuit, a pad and a pulling resistant device. The I/O circuit is for inputting or outputting a signal. The pulling resistant device has a plurality of resistant elements electrically connected between the I/O circuit and the pad, for forming a resistance value.

Claims

1. An I/O buffer, comprising:

an I/O circuit, for inputting or outputting a signal;

a pad; and

a pulling resistant device, having a plurality of resistant elements electrically connected between the I/O circuit and the pad, for forming a resistance value.

2. The I/O buffer of claim 1, wherein the resistant elements are electrically connected in series or in parallel.

3. The I/O buffer of claim 1, wherein resistant elements are segmented in space.

4. The I/O buffer of claim 1, wherein the I/O circuit is a high voltage tolerant I/O circuit.

5. The I/O buffer of claim 1, wherein the I/O circuit comprises a PMOS transistor and an NMOS transistor connected in series, one end of the pulling resistant device is directly connected to a drain of the PMOS transistor and a drain of the NMOS transistor, and the other end of the pulling resistant device is directly connected to the pad.

6. The I/O buffer of claim 1, wherein the I/O circuit comprises a PMOS transistor and an NMOS transistor, one end of the pulling resistant device is directly connected to a drain of the PMOS transistor, and the other end of the pulling resistant device is directly connected to a drain of the NMOS transistor.

7. A semiconductor structure of an I/O buffer, comprising:

a substrate;

an active circuit, formed on the substrate;

a silicon oxide layer on the substrate;

a patterned poly-silicon layer on the silicon oxide layer, the patterned poly-silicon layer having a first part and a second part;

a patterned silicide layer on the patterned poly-silicon layer to expose at least part of the patterned poly-silicon layer;

a dielectric layer on the patterned poly-silicon layer and the silicide layer, the dielectric layer having a plurality of contacts; and

a patterned metal layer on the dielectric layer for contacting the active circuit and the patterned silicide layer via the contacts;

wherein the patterned metal layer is separated into a first part, a second part, and a third part, and the second part is between the first part and the third part, where the first part of patterned metal layer contacts the patterned silicide layer on the first part of the patterned poly-silicon layer, the third part of patterned metal layer contacts the patterned silicide layer on the second part of the patterned poly-silicon layer, and the second part of patterned metal layer contacts both the patterned silicide layer on the first part and second part of the patterned poly-silicon layer.

8. A semiconductor structure of an I/O buffer, comprising:

a substrate;

an active circuit, formed on the substrate;

a silicon oxide layer on the substrate;

a patterned poly-silicon layer on the silicon oxide layer;

a patterned silicide layer on the patterned poly-silicon layer to expose at least part of the patterned poly-silicon layer and separated in at least two parts;

a dielectric layer on the patterned poly-silicon layer and the silicide layer, the dielectric layer having a plurality of contacts; and

a patterned metal layer on the dielectric layer for contacting the active circuit and the patterned silicide layer via the contacts;

wherein the patterned silicide layer is separated into a first part, a second part, and a third part, and the second part is between the first part and the third part, the patterned metal layer is separated into a first part and a second part, where the first part of patterned metal layer contacts the first part of the patterned silicide layer, and the second part of patterned metal layer contacts the third part of the patterned silicide layer.