AUTOMATIC PHASE-DETECTION CIRCUIT FOR CLOCKS WITH KNOWN RATIOS

• US 20090184735A1
• Filed: 01/23/2008
• Published: 07/23/2009
• Est. Priority Date: 01/23/2008
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Wicki, Thomas, Daga, Bharat
• Granted Patent: US 7,609,092 B2
• Time in Patent Office: Days
• US Class Current: 327/9
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: H03K 5/26 the characteristic being duration, interval, position, frequency, or sequence

Abstract

An automatic phase detection circuit for generating an internal synchronization signal when two clock input signals achieve a certain phase relationship. No external reference signal is required. The logic state of one clock is sampled on the active edge of the other clock and stored in a shift register. The content of the shift register is compared to a pre-defined signature and a sync signal is generated when the content matches the pre-defined signature. A mask register may be used to define which bits of the shift register and pre-defined signature are compared.

Claims

1. An automatic phase detection circuit for clocks, comprising:

a sequential state element having a data input, a first clock input and a data output;

a first clock operably coupled to the data input;

a second clock operably coupled to the first clock input;

a serial input, parallel output shift register having a second clock input operably coupled to the second clock and the serial input operably coupled to the data output;

a signature register configured to store a repetitive portion of an output sequence of the data output;

a comparator operably coupled to the parallel output of the shift register and operably coupled to the signature register, the comparator configured to compare a content of the signature register and a content of the shift register; and

wherein the comparator generates a pulse when the content of the signature register and the content of the shift register match.

2. The automatic phase detection circuit of claim 1, wherein a first frequency of the first clock and a second frequency of the second clock have a phase relationship that repeats every D first clock cycles and every N second clock cycles such that a clock ratio of the second clock frequency to the first clock frequency is equal to N/D.

3. The automatic phase detection circuit of claim 2, wherein the shift register, comparator and signature register each are of length N bits.

4. The automatic phase detection circuit of claim 1, further comprising a mask register circuit coupled to the comparator to mask a portion of the comparison such that the masked portion is not used to generate the pulse.

5. The automatic phase detection circuit of claim 4, wherein masking a portion of the comparison is performed on a bit level.

6. The automatic phase detection circuit of claim 2, wherein the repetitive portion of the output sequence is determined as that portion of the output sequence beginning when an active edge of the first clock and an active edge of the second clock align and ending after N second clock cycles.

7. The automatic phase detection circuit of claim 1, wherein the repetitive portion of the output sequence is rotated in the signature register.

8. A method of performing automatic phase detection for clocks with a certain frequency ratio, the method comprising:

receiving a first clock signal and a second clock signal;

identifying a repetitive sequence that occurs when an active edge of the first clock signal is used to sample a logic state of the second clock signal;

sampling the second clock signal on each active edge of the first clock signal to obtain a sample sequence; and

generating a sync pulse when the sample sequence matches the repetitive sequence.

9. The method of claim 8, wherein the repetitive sequence repeats after a finite number of second clock signal cycles.

10. The method of claim 8, wherein the operation of sampling comprises using a D-type flip-flop to sample the second clock signal on each active edge of the first clock signal.

11. The method of claim 8, further comprising storing the repetitive sequence in a register.

12. The method of claim 8, further comprising storing the sample sequence in a serial in, parallel out shift register.

13. The method of claim 8, wherein the generating operation further comprises performing a comparison of the sample sequence with the repetitive logic sequence on a bit by bit basis.

14. The method of claim 13, further comprising masking one or more bits of the comparison.

15. A programmable clock module having a first clock input and a second clock input, comprising:

a sequential state element having a data input operably coupled to the first clock input, a data output and a clock input operably coupled to the second clock input;

a serial input port, parallel output port n-bit shift register having a clock input port, the clock input port operably coupled to the second clock input and the serial input port operably coupled to the data output;

an n-bit comparator operably coupled to the shift register and configured to compare a content of the shift register with a pre-defined signature;

an n-bit mask register operably coupled to the comparator and configured to mask a portion of the comparison; and

wherein the comparator generates a pulse when the content of the shift register matches the pre-defined signature.

16. The programmable clock module of claim 15, wherein the pre-defined signature is stored in a signature register, the pre-defined signature is a repetitive pattern and the mask register is configured to mask corresponding unused bits of the signature register.

17. The programmable clock module of claim 16, wherein the repetitive pattern is a length r-bits, r is less than or equal to n, and the n-r high order bits of the mask register are configured to mask the corresponding bits of the comparison.

18. The programmable clock module of claim 16, wherein the repetitive pattern is a repetitive portion of a logic state pattern determined by sampling a logic state of the first clock input on each active edge of the second clock input.

19. The programmable clock module of claim 18, wherein a clock ratio of the second clock frequency to the first clock frequency is F/S and wherein the logic state pattern repeats every F second clock cycles and every S first clock cycles.

20. The programmable clock module of claim 19, wherein n is greater than or equal to F.

21. The programmable clock module of claim 16, wherein the pre-defined signature is shifted to a higher location in the signature register.

22. The programmable clock module of claim 16, wherein the pre-defined signature is replicated to fill all bits of the signature register.