A/D CONVERTING APPARATUS

• US 20090184857A1
• Filed: 01/06/2009
• Published: 07/23/2009
• Est. Priority Date: 01/07/2008
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Furuta, Masanori, Itakura, Tetsuro, Ito, Tomohiko, Yamaji, Takafumi
• Granted Patent: US 7,884,749 B2
• Time in Patent Office: Days
• US Class Current: 341/156
• CPC Class Codes: H03M 1/1215 using time-division multiplexing
• CPC Class Codes: H03M 1/162 the steps being performed sequentially in a single stage, i.e. recirculation type H03M1/161 takes precedence
• CPC Class Codes: H03M 1/164 the steps being performed sequentially in series-connected stages H03M1/161 takes precedence
• CPC Class Codes: H03M 1/468 in which the input S/H circuit is merged with the feedback DAC array

Abstract

An A/D converting apparatus includes a first A/D converter to sample an analog input signal having a D/A converter to generate a comparative signal for successive comparison with the analog input signal, a signal generator generate a differential signal between the analog input signal and the comparative signal, and a comparator to compare the comparative signal with a standard value to generate a first digital signal exhibiting high-order bit; an amplifier to amplify the differential signal to generate a residue signal; and a second A/D converter to sample the residue signal to generate a second digital signal exhibiting low-order bit.

Claims

1. An A/D converting apparatus, comprising:

a first A/D converter to sample an analog input signal having a D/A converter to generate a comparative signal for successive comparison with the analog input signal, a signal generator to generate a differential signal between the analog input signal and the comparative signal, and a comparator to compare the comparative signal with a standard value to generate a first digital signal exhibiting high-order bit;

an amplifier to amplify the differential signal to generate a residue signal; and

a second A/D converter to sample the residue signal to generate a second digital signal exhibiting low-order bit.

2. The apparatus of claim 1, further comprising a timing controller to suspend a sampling operation of the first A/D converter while the second A/D converter samples the residue signal.

3. The apparatus of claim 1,

wherein the first A/D converter holds the analog input signal sampled for a predetermined period of time.

4. The A/D converting apparatus of claim 1,

wherein the D/A converter has a plurality of capacitors connected in parallel one another.

5. The apparatus of claim 4,

wherein ratios in capacitance of the plurality of capacitors are set to 1/2, 1/4, 1/8, 1/16, and 1/16.

6. The apparatus of claim 4, further comprising a plurality of switches to apply one of the analog input signal, a reference voltage or a grounded voltage to one end of the capacitors.

7. An A/D converting apparatus, comprising:

a D/A converter to generate a comparative signal for successive comparison with an input signal;

a signal generator to generate a differential signal between the input signal and the comparative signal;

a comparator to compare the comparative signal with a standard value to generate a digital signal;

an amplifier to amplify the differential signal to generate a residue signal; and

a switch to send either an analog input signal or the residue signal to the D/A converter.

8. The apparatus of claim 7, further comprising a timing controller to control the D/A converter to generate a second comparative signal based on a residue signal obtained by amplifying a differential signal of a first comparative signal after the D/A converter generates the first comparative signal based on the analog input signal and the comparator generates a first digital signal based on the first comparative signal.

9. An A/D converting apparatus, comprising:

a first A/D converter to sample an analog input signal at a first timing to generate a first analog signal, the first A/D converter having a first D/A converter to generate a first comparative signal for successive comparison with the first analog signal, a first signal generator to generate a first differential signal between the first analog signal and the first comparative signal, and a first comparator to compare the first comparative signal with a first standard value to generate a first digital signal exhibiting a first high-order bit;

a second A/D converter to sample the analog input signal at a second timing different from the first timing to generate a second analog signal, the second A/D converter having a second D/A converter to generate a second comparative signal for successive comparison with the second analog signal, a second signal generator to generate a second differential signal between the second analog signal and the second comparative signal, and a second comparator to compare the second comparative signal with a second standard value to generate a second digital signal exhibiting a second high-order bit;

a third D/A converter to hold the first differential signal and the second differential signal to implement analog conversion;

an amplifier to amplify the first differential signal and the second differential signal which are analog-converted to generate a first residue signal and a second residue signal;

a third A/D converter to sample the first residue signal to generate a third digital signal exhibiting a first low-order bit corresponding to the first high-order bit; and

a fourth A/D converter to sample the second residue signal to generate a fourth digital signal exhibiting a second low-order bit corresponding to the second high-order bit.