PIXEL STRUCTURE OF LIQUID CRYSTAL DISPLAY PANEL AND METHOD OF MAKING THE SAME

• US 20090185089A1
• Filed: 05/06/2008
• Published: 07/23/2009
• Est. Priority Date: 01/17/2008
• Status: Active Grant

• Current Assignee: AU Optronics Corporation
• Original Assignee: AU Optronics Corporation
• Inventors: Huang, Kuo-Yu, Chang, Ke-Chih
• Granted Patent: US 7,755,735 B2
• Time in Patent Office: Days
• US Class Current: 349/38
• CPC Class Codes: G02F 1/13606 having means for reducing parasitic capacitance
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 2201/40 Arrangements for improving the aperture ratio
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/78633 with a light shield

Abstract

A pixel structure of a liquid crystal display panel includes a scan line, a data line, a thin film transistor (TFT), a pixel electrode, a light-shielding pattern, and a common line. The data line includes a first data line section and a second data line section composed respectively of the first material layer and second material layer and electrically connected to each other through a plurality of contact plugs. In addition, the pixel electrode is electrically connected to a drain of the TFT, and the light-shielding pattern, which is a floating metal, is disposed over the first data line section. The common line, the light-shielding pattern, and the second data line section are composed of the same material layer.

Claims

1. A method of forming a pixel structure, comprising:

providing a substrate;

forming a first patterned conductive layer on the substrate, wherein the first patterned conductive layer comprises a scan line, a gate, and a first data line section, wherein the gate is electrically connected to the scan line;

forming an insulating layer on the first patterned conductive layer, wherein the insulating layer comprises a plurality of first contact holes disposed over the first data line section;

forming a second patterned conductive layer on the insulating layer and filling the second patterned conductive layer into the first contact holes to form a plurality of first contact plugs, wherein the second patterned conductive layer comprises a second data line section, a source, a drain, and a light-shielding pattern, wherein the second data line section is electrically connected to the source, and electrically connected to the first data line section via the first contact plugs, the light-shielding pattern is a floating metal, partially overlapping the first data line section;

forming a dielectric layer on the second patterned conductive layer; and

forming a pixel electrode on the dielectric layer, wherein the pixel electrode is electrically connected to the drain.

2. The method of claim 1, further comprising forming a common line in the step of forming the second patterned conductive layer, wherein the common line and the light-shielding pattern is gapped with a space.

3. The method of claim 2, wherein the common line, the pixel electrode, and the dielectric layer disposed therebetween compose a first storage capacitor.

4. The method of claim 1, wherein the first patterned conductive layer further comprises an electrode pattern electrically connected to the drain.

5. The method of claim 4, wherein the electrode pattern, the common line, and the insulating layer disposed therebetween compose a second storage capacitor.

6. The method of claim 4, wherein the insulating layer further comprises a second contact hole disposed between the drain and the electrode pattern, and the step of forming the second patterned conductive layer further comprises filling the drain into the second contact hole to form a second contact plug to electrically connect the electrode pattern and the drain.

7. The method of claim 6, wherein the dielectric layer further comprises a third contact hole corresponding to the electrode pattern, the step of forming the pixel electrode further comprises filling the pixel electrode into the third contact hole to electrically connect to the electrode pattern, and the pixel electrode is electrically connected to the drain via the electrode pattern and the second contact plug.

8. The method of claim 1, wherein the dielectric layer further comprises a third contact hole disposed on the drain, and the step of forming the pixel electrode further comprises filling the pixel electrode into the third contact hole to electrically connected to the drain.

9. The method of claim 1, wherein the first data line section at least comprises a plurality of wide blocks, and the plurality of first contact holes are disposed over and corresponding to the wide blocks.

10. A pixel structure, comprising:

a substrate;

a first patterned conductive layer disposed on the substrate, the first patterned conductive layer comprising a scan line, a gate electrically connected to the scan line, and a first data line section;

an insulating layer disposed on the first patterned conductive layer, wherein the insulating layer comprises a plurality of first contact holes;

a second patterned conductive layer disposed on the insulating layer, the second patterned conductive layer comprising a second data line section, a source electrically connected to the second data line section, a drain, a common line, and a light-shielding pattern, wherein the light-shielding pattern is a floating metal, partially overlapping the first data line section;

a plurality of first contact plugs disposed in the first contact holes, wherein the second data line section is electrically connected to the first data line section via the first contact plugs;

a pixel electrode electrically connected to the drain; and

at least a dielectric layer disposed between the second patterned conductive layer and the pixel electrode.

11. The pixel structure of claim 10, wherein the common line and the light-shielding pattern is gapped with a space.

12. The pixel structure of claim 10, wherein the common line, the pixel electrode, and the dielectric layer disposed therebetween compose a first storage capacitor.

13. The pixel structure of claim 10, wherein the first patterned conductive layer further comprises an electrode pattern electrically connected to the drain.

14. The pixel structure of claim 13, wherein the electrode pattern, the common line, and the insulating layer disposed therebetween compose a second storage capacitor.

15. The pixel structure of claim 13, wherein the insulating layer further comprises a second contact hole disposed between the drain and the electrode pattern, and a second contact plug disposed in the second contact hole, and the electrode pattern is electrically connected to the drain via the second contact plug.

16. The pixel structure of claim 15, wherein the dielectric layer further comprises a third contact hole corresponding to the electrode pattern, the pixel electrode is filling into the third contact hole and electrically connected to the electrode pattern, and the pixel electrode is electrically connected to the drain via the electrode pattern and the second contact plug.

17. The pixel structure of claim 10, wherein the dielectric layer further comprises a third contact hole corresponding to the drain, and the pixel electrode is filling into the third contact hole and electrically connected to the drain.

18. The pixel structure of claim 10, wherein the dielectric layer comprises a single-layered dielectric layer or a multi-layered dielectric layer.

19. A pixel structure, comprising:

a scan line;

a data line crisscrossed with the scan line, the data line at least comprising a first data line section and a second data line section, wherein the first data line section comprises a first material layer, the second data line section comprises a second material layer, the first data line section and the second data line section are electrically connected together via a plurality of contact plugs;

a thin film transistor electrically connected to the scan line and the second data line section;

a light-shielding pattern disposed over the first data line section, the light-shielding pattern being a floating metal; and

a common line, parallel to the scan line, disposed between the light-shielding pattern and the thin film transistor, wherein the common line, the light-shielding pattern and the second data line section are made of a same material layer.

20. The pixel structure of claim 19, wherein the common line and the light-shielding pattern is gapped with a space.

21. The pixel structure of claim 19, further comprising a dielectric layer disposed between the common line and the pixel electrode, and wherein the common line, the pixel electrode, and the dielectric layer disposed therebetween compose a first storage capacitor.

22. The pixel structure of claim 19, further comprising an electrode pattern made of a same material as the first data line section, and wherein the electrode pattern is electrically connected to the drain.

23. The pixel structure of claim 22, further comprising an insulating layer disposed between the electrode pattern and the common line, and wherein the electrode pattern, the common line, and the insulating layer disposed therebetween compose a second storage capacitor.

24. The pixel structure of claim 23, wherein the insulating layer further comprises a second contact hole disposed between the drain and the electrode pattern, and a second contact plug disposed in the second contact hole, and the electrode pattern is electrically connected to the drain via the second contact plug.

25. The pixel structure of claim 24, wherein the dielectric layer further comprises a third contact hole corresponding to the electrode pattern, the pixel electrode is filling into the third contact hole and electrically connected to the electrode pattern, and the pixel electrode is electrically connected to the drain via the electrode pattern and the second contact plug.

26. The pixel structure of claim 21, wherein the dielectric layer further comprises a third contact hole corresponding to the drain, and the pixel electrode is filling into the third contact hole and electrically connected to the drain.

27. The pixel structure of claim 21, wherein the dielectric layer comprises a single-layered dielectric layer or a multi-layered dielectric layer.

28. A liquid crystal display panel, comprising:

a first substrate comprising the pixel structure of claim 19;

a second substrate opposite to the first substrate, wherein the second substrate comprises a patterned light-shielding matrix disposed over and corresponding to the thin film transistor, and a color filter unit disposed over and corresponding to the light-shielding pattern; and

a liquid crystal layer disposed between the first substrate and the second substrate.