Regenerative Building Block and Diode Bridge Rectifier and Methods

• US 20090185404A1
• Filed: 01/23/2009
• Published: 07/23/2009
• Est. Priority Date: 09/26/2007
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: Lakota Technologies, Inc. (2-Infinity, Inc.)
• Inventors: Ankoudinov, Alexei, Rodov, Vladimir
• Granted Patent: US 8,421,118 B2
• Time in Patent Office: Days
• US Class Current: 363/126
• CPC Class Codes: H01L 27/0817 Thyristors only
• CPC Class Codes: H01L 29/0646 PN junctions
• CPC Class Codes: H01L 29/66075 of devices having semiconductor bodies comprising group 14 or group 13/15 materials comprising semiconducting carbon H01L29/66015; comprising crystalline silicon carbide H01L29/66053
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/861 Diodes

Abstract

A rectifier building block has four electrodes: source, drain, gate and probe. The main current flows between the source and drain electrodes. The gate voltage controls the conductivity of a narrow channel under a MOS gate and can switch the RBB between OFF and ON states. Used in pairs, the RBB can be configured as a three terminal half-bridge rectifier which exhibits better than ideal diode performance, similar to synchronous rectifiers but without the need for control circuits. N-type and P-type pairs can be configured as a full bridge rectifier. Other combinations are possible to create a variety of devices.

Claims

1. A semiconductor device operable as a half bridge comprising

a first drain contact, operatively coupled to a first gate region, a first source region, and a first probe region,

a second drain contact, operatively coupled to a second gate region, a second source region, and a second probe region,

a first source contact,

the first probe region connected to the second gate region,

the first gate region connected to the second probe region,

the first source region connected to the second source region, and to the first source contact.

2. A method for manufacturing a semiconductor device comprising the steps of

depositing first and second source structures in a substrate,

depositing a gate structure on a substrate,

attaching a drain contact on a substrate, and

depositing a probe structure between the first and second source structures for controlling the current between the source and drain structures.